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soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled 

Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it.  Otherwise, disable the
PCI device if it has been enabled in devicetree.

To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.

Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2018-03-26 02:25:07 -07:00 committed by Patrick Georgi
parent 4c8fbc0658
commit 2410cd9379
3 changed files with 8 additions and 3 deletions
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1
src/soc/intel/cannonlake/Kconfig
View File

@ -70,6 +70,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_TIMER
select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SSE2 select SSE2

9
src/soc/intel/cannonlake/chip.c
View File

@ -19,6 +19,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <soc/intel/common/vbt.h> #include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -180,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{ {
int i; int i;
FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_CONFIG *params = &supd->FspsConfig;
const struct device *dev = SA_DEV_ROOT; struct device *dev = SA_DEV_ROOT;
config_t *config = dev->chip_info; config_t *config = dev->chip_info;
/* Parse device tree and enable/disable devices */ /* Parse device tree and enable/disable devices */
@ -262,7 +263,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
} }
} }
params->XdciEnable = config->XdciEnable; /* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
/* PCI Express */ /* PCI Express */
for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {

1
src/soc/intel/cannonlake/chip.h
View File

@ -124,7 +124,6 @@ struct soc_intel_cannonlake_config {
/* USB related */ /* USB related */
struct usb2_port_config usb2_ports[16]; struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10]; struct usb3_port_config usb3_ports[10];
uint8_t XdciEnable;
uint8_t SsicPortEnable; uint8_t SsicPortEnable;
/* Wake Enable Bitmap for USB2 ports */ /* Wake Enable Bitmap for USB2 ports */
uint16_t usb2_wake_enable_bitmap; uint16_t usb2_wake_enable_bitmap;