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mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports 

This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.

BUG=b:149186922

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-05-07 14:29:13 -07:00 committed by Aaron Durbin
parent cc35f723fd
commit 2412924bc7
1 changed files with 15 additions and 0 deletions
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15
src/mainboard/google/volteer/Kconfig
View File

@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_VOLTEER
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select PCIEXP_HOTPLUG
select SOC_INTEL_TIGERLAKE select SOC_INTEL_TIGERLAKE
if BOARD_GOOGLE_BASEBOARD_VOLTEER if BOARD_GOOGLE_BASEBOARD_VOLTEER
@ -66,6 +67,20 @@ config MAX_CPUS
int int
default 8 default 8
# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569)
# Revision 0.7.6 Section 7.2.5.1.5
config PCIEXP_HOTPLUG_BUSES
int
default 42
config PCIEXP_HOTPLUG_MEM
hex
default 0xc200000 # 194 MiB
config PCIEXP_HOTPLUG_PREFETCH_MEM
hex
default 0x1c000000 # 448 MiB
config TPM_TIS_ACPI_INTERRUPT config TPM_TIS_ACPI_INTERRUPT
int int
default 21 # GPE0_DW0_21 (GPP_C21) default 21 # GPE0_DW0_21 (GPP_C21)