post_code: add post code for memory error

Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

Documentation/POSTCODES

@@ -19,6 +19,7 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
 0xe0 Boot media (e.g. SPI ROM) is corrupt
 0xe1 Resource stored within CBFS is corrupt
 0xe2 Vendor binary (e.g. FSP) generated a fatal error
+0xe3 RAM could not be initialized
 0xf8 Entry into elf boot
 0xf3 Jumping to payload
 

src/drivers/intel/fsp1_1/raminit.c

@@ -130,7 +130,8 @@ void raminit(struct romstage_params *params)
 
 	printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
 	if (status != EFI_SUCCESS)
-		die("ERROR - FspMemoryInit failed to initialize memory!\n");
+		die_with_post_code(POST_RAM_FAILURE,
+			"ERROR - FspMemoryInit failed to initialize memory!\n");
 
 	/* Locate the FSP reserved memory area */
 	fsp_reserved_bytes = 0;

src/drivers/intel/fsp2_0/memory_init.c

@@ -316,7 +316,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
 	fsp_handle_reset(status);
 	if (status != FSP_SUCCESS) {
 		printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status);
-		die("FspMemoryInit returned an error!\n");
+		die_with_post_code(POST_RAM_FAILURE,
+			"FspMemoryInit returned an error!\n");
 	}
 
 	do_fsp_post_memory_init(s3wake, fsp_version);

src/include/console/post_codes.h

@@ -340,6 +340,14 @@
  */
 #define POST_INVALID_VENDOR_BINARY		0xe2
 
+/**
+ * \brief RAM failure
+ *
+ * Set if RAM could not be initialized.  This includes RAM is missing,
+ * unsupported RAM configuration, or RAM failure.
+ */
+#define POST_RAM_FAILURE			0xe3
+
 /**
  * \brief TPM failure
  *