sb/intel/i82801gx: Move CIR init to a common place

Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.

Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>

src/mainboard/apple/macbook21/romstage.c

@@ -195,31 +195,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	/* next step only on ich7m b0 and later: */
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/asrock/g41c-gs/romstage.c

@@ -36,7 +36,6 @@
 
 static void mb_lpc_setup(void)
 {
-	u32 reg32;
 	/* Set the value for GPIO base address register and enable GPIO. */
 	pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
 	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -65,11 +64,7 @@ static void mb_lpc_setup(void)
 	RCBA8(OIC) = 0x03;
 	RCBA8(OIC);
 
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 5);
-	RCBA32(GCS) = reg32;
-
-	RCBA32(CG) = 0x00000001;
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/asus/p5gc-mx/romstage.c

@@ -145,31 +145,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030509;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/asus/p5qpl-am/romstage.c

@@ -131,7 +131,6 @@ static int setup_sio_gpio(void)
 
 static void mb_lpc_setup(void)
 {
-	u32 reg32;
 	/* Set the value for GPIO base address register and enable GPIO. */
 	pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
 	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -142,10 +141,7 @@ static void mb_lpc_setup(void)
 	RCBA8(0x31ff) = 0x03;
 	RCBA8(0x31ff);
 
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 5);
-	RCBA32(GCS) = reg32;
-	RCBA32(CG) = 0x00000001;
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/foxconn/g41s-k/romstage.c

@@ -67,7 +67,8 @@ static void mb_lpc_setup(void)
 	RCBA8(OIC);
 
 	RCBA32(FD) |= FD_INTLAN;
-	RCBA32(CG) = 0x00000001;
+
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/getac/p470/romstage.c

@@ -204,31 +204,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
-	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c

@@ -107,31 +107,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030509;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/gigabyte/ga-g41m-es2l/romstage.c

@@ -96,16 +96,7 @@ static void mb_gpio_init(void)
 	RCBA8(OIC) = 0x03;
 	RCBA8(OIC);
 
-	RCBA32(GCS) = 0x00190464;
-	RCBA32(CG) = 0x00000000;
-	RCBA32(0x3430) = 0x00000001;
-	RCBA32(0x3e00) = 0xff000001;
-	RCBA32(0x3e08) = 0x00000080;
-	RCBA32(0x3e0c) = 0x00800000;
-	RCBA32(0x3e40) = 0xff000001;
-	RCBA32(0x3e48) = 0x00000080;
-	RCBA32(0x3e4c) = 0x00800000;
-	RCBA32(0x3f00) = 0x0000000b;
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/ibase/mb899/romstage.c

@@ -169,31 +169,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/intel/d945gclf/romstage.c

@@ -89,31 +89,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(0x3410);
-	reg32 |= (1 << 6);
-	RCBA32(0x3410) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/intel/dg41wv/romstage.c

@@ -32,7 +32,6 @@
 
 static void mb_lpc_setup(void)
 {
-	u32 reg32;
 	/* Set the value for GPIO base address register and enable GPIO. */
 	pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
 	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -55,10 +54,7 @@ static void mb_lpc_setup(void)
 	RCBA8(0x31ff) = 0x03;
 	RCBA8(0x31ff);
 
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 5);
-	RCBA32(GCS) = reg32;
-	RCBA32(CG) = 0x00000001;
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/kontron/986lcd-m/romstage.c

@@ -212,31 +212,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	/* next step only on ich7m b0 and later: */
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/lenovo/t60/romstage.c

@@ -129,31 +129,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/lenovo/thinkcentre_a58/romstage.c

@@ -30,7 +30,6 @@
 
 static void mb_lpc_setup(void)
 {
-	u32 reg32;
 	/* Set the value for GPIO base address register and enable GPIO. */
 	pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
 	pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10);
@@ -41,10 +40,7 @@ static void mb_lpc_setup(void)
 	RCBA8(0x31ff) = 0x03;
 	RCBA8(0x31ff);
 
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 5);
-	RCBA32(GCS) = reg32;
-	RCBA32(CG) = 0x00000001;
+	ich7_setup_cir();
 }
 
 static void ich7_enable_lpc(void)

src/mainboard/lenovo/x60/romstage.c

@@ -129,31 +129,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	// next step only on ich7m b0 and later:
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 void mainboard_romstage_entry(void)

src/mainboard/roda/rk886ex/romstage.c

@@ -168,31 +168,7 @@ static void early_ich7_init(void)
 	reg32 |= (1 << 31) | (1 << 27);
 	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 
-	RCBA32(0x0088) = 0x0011d000;
-	RCBA16(0x01fc) = 0x060f;
-	RCBA32(0x01f4) = 0x86000040;
-	RCBA32(0x0214) = 0x10030549;
-	RCBA32(0x0218) = 0x00020504;
-	RCBA8(0x0220) = 0xc5;
-	reg32 = RCBA32(GCS);
-	reg32 |= (1 << 6);
-	RCBA32(GCS) = reg32;
-	reg32 = RCBA32(0x3430);
-	reg32 &= ~(3 << 0);
-	reg32 |= (1 << 0);
-	RCBA32(0x3430) = reg32;
-	RCBA16(0x0200) = 0x2008;
-	RCBA8(0x2027) = 0x0d;
-	RCBA16(0x3e08) |= (1 << 7);
-	RCBA16(0x3e48) |= (1 << 7);
-	RCBA32(0x3e0e) |= (1 << 7);
-	RCBA32(0x3e4e) |= (1 << 7);
-
-	/* next step only on ich7m b0 and later: */
-	reg32 = RCBA32(0x2034);
-	reg32 &= ~(0x0f << 16);
-	reg32 |= (5 << 16);
-	RCBA32(0x2034) = reg32;
+	ich7_setup_cir();
 }
 
 static void init_artec_dongle(void)

src/northbridge/intel/pineview/early_init.c

@@ -135,26 +135,8 @@ static void early_misc_setup(void)
 	pci_write_config8(LPC, 0x8, 0x1d);
 	pci_write_config8(LPC, 0x8, 0x0);
 	RCBA32(0x3410) = 0x00020465;
-	RCBA32(0x88) = 0x0011d000;
-	RCBA32(0x1fc) = 0x60f;
-	RCBA32(0x1f4) = 0x86000040;
-	RCBA32(0x214) = 0x10030509;
-	RCBA32(0x218) = 0x00020504;
-	RCBA32(0x220) = 0xc5;
-	RCBA32(0x3430) = 0x1;
-	RCBA32(0x2027) = 0x38f6a70d;
-	RCBA16(0x3e08) = 0x0080;
-	RCBA16(0x3e48) = 0x0080;
-	RCBA32(0x3e0e) = 0x00000080;
-	RCBA32(0x3e4e) = 0x00000080;
-	RCBA32(0x2034) = 0xb24577cc;
-	RCBA32(0x1c) = 0x03128010;
-	RCBA32(0x2010) = 0x400;
-	RCBA32(0x3400) = 0x4;
-	RCBA32(0x2080) = 0x18006007;
-	RCBA32(0x20a0) = 0x18006007;
-	RCBA32(0x20c0) = 0x18006007;
-	RCBA32(0x20e0) = 0x18006007;
+
+	ich7_setup_cir();
 
 	pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
 	pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);

src/southbridge/intel/i82801gx/Makefile.inc

@@ -35,5 +35,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 smm-y += smihandler.c
 
 romstage-y += early_smbus.c
+romstage-y += early_cir.c
 
 endif

src/southbridge/intel/i82801gx/early_cir.c

@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include "i82801gx.h"
+
+/* Chipset Initialization Registers magic */
+void ich7_setup_cir(void)
+{
+	uint32_t reg32;
+	uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID);
+	uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	/* Although bit 6 is set, it is not read back */
+	RCBA32(0x0214) = 0x10030549;
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(GCS);
+	reg32 |= (1 << 6);
+	RCBA32(GCS) = reg32;
+	RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+
+	/* Only on mobile variants of revision b0 or later */
+	switch (pci_id) {
+	case 0x27b9:
+	case 0x27bc:
+	case 0x27bd:
+		if (revision >= 2) {
+			reg32 = RCBA32(0x2034);
+			reg32 &= ~(0x0f << 16);
+			reg32 |= (5 << 16);
+			RCBA32(0x2034) = reg32;
+		}
+	}
+}

src/southbridge/intel/i82801gx/i82801gx.h

@@ -48,6 +48,7 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
 int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
 		const u8 *buf);
+void ich7_setup_cir(void);
 #endif
 
 #define MAINBOARD_POWER_OFF	0