boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2 chipsets in order to save memory configuration in flash. Convert both of these chipsets to use the boot state machine callbacks to perform the saving of the memory configuration. Change-Id: I697e5c946281b85a71d8533437802d7913135af3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3137 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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40131cfa46
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243aa44b74
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@ -159,7 +159,6 @@ void *cbmem_find(u32 id);
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/* Ramstage only functions. */
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void cbmem_list(void);
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void cbmem_arch_init(void);
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void __attribute__((weak)) cbmem_post_handling(void);
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void cbmem_print_entry(int n, u32 id, u64 start, u64 size);
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#else
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static inline void cbmem_arch_init(void) {}
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@ -37,7 +37,6 @@
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#if CONFIG_HAVE_ACPI_RESUME
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#include <arch/acpi.h>
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#endif
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#include <cbmem.h>
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#include <timestamp.h>
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#if BOOT_STATE_DEBUG
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@ -186,9 +185,6 @@ static boot_state_t bs_os_resume(void *wake_vector)
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static boot_state_t bs_write_tables(void *arg)
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{
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if (cbmem_post_handling)
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cbmem_post_handling();
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timestamp_add_now(TS_WRITE_TABLES);
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/* Now that we have collected all of our information
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@ -237,8 +237,6 @@ struct mrc_data_container {
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struct mrc_data_container *find_current_mrc_cache(void);
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#if !defined(__PRE_RAM__)
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void update_mrc_cache(void);
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#include "gma.h"
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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#endif
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@ -19,6 +19,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cbfs.h>
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#include <ip_checksum.h>
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@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache
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return mrc_cache;
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}
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void update_mrc_cache(void)
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static void update_mrc_cache(void *unused)
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{
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printk(BIOS_DEBUG, "Updating MRC cache data.\n");
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struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
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@ -222,6 +223,11 @@ void update_mrc_cache(void)
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flash->write(flash, to_flash_offset(cache),
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current->mrc_data_size + sizeof(*current), current);
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}
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BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
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BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
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update_mrc_cache, NULL),
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};
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#endif
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struct mrc_data_container *find_current_mrc_cache(void)
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@ -53,11 +53,6 @@ int bridge_silicon_revision(void)
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return bridge_revision_id;
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}
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void cbmem_post_handling(void)
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{
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update_mrc_cache();
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}
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static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 pciexbar_reg;
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@ -19,6 +19,7 @@
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#include <stdint.h>
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#include <string.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cbfs.h>
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#include <ip_checksum.h>
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@ -153,7 +154,7 @@ static struct mrc_data_container *find_next_mrc_cache
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return mrc_cache;
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}
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void update_mrc_cache(void)
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static void update_mrc_cache(void *unused)
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{
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printk(BIOS_DEBUG, "Updating MRC cache data.\n");
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struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
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@ -222,6 +223,11 @@ void update_mrc_cache(void)
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flash->write(flash, to_flash_offset(cache),
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current->mrc_data_size + sizeof(*current), current);
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}
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BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = {
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BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
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update_mrc_cache, NULL),
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};
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#endif
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struct mrc_data_container *find_current_mrc_cache(void)
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@ -60,11 +60,6 @@ int bridge_silicon_revision(void)
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 384;
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void cbmem_post_handling(void)
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{
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update_mrc_cache();
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}
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static int get_pcie_bar(u32 *base, u32 *len)
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{
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device_t dev;
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@ -233,8 +233,6 @@ struct mrc_data_container {
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struct mrc_data_container *find_current_mrc_cache(void);
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#if !defined(__PRE_RAM__)
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void update_mrc_cache(void);
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#include "gma.h"
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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#endif
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