GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/x4x: Unroll programming RCOMP data group 

The RCOMP data group is special and is programmed differently. Prepare
to simplify the code by programming it outside of the loop. Subsequent
commits will simplify the logic even further, then clean up cosmetics.

The special DDR3 case in the loop overwrites the command group strength
multiplier value. It doesn't need to be programmed for each RCOMP group.
Add a comment to justify not programming this register while programming
the settings for the RCOMP data group.

Tested on Asus P5QL PRO (DDR2), still boots.

Change-Id: I5c2484f48e3c07e8e787b1894932e342e8e8a75c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2021-01-13 17:28:31 +01:00 committed by Patrick Georgi
parent 6b17794dda
commit 244391a075
1 changed files with 19 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -1093,20 +1093,25 @@ static void prog_rcomp(struct sysinfo *s)
} }
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
for (j = 0; j < 6; j++) { /* RCOMP data group is special, program it separately */
if (j == 0) { MCHBAR32_AND_OR(0x400*i + 0x31c, ~0xff000,
MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000,
0xaa000); 0xaa000);
MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff, MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
0x6666); 0x6666);
for (k = 0; k < 8; k++) { for (k = 0; k < 8; k++) {
MCHBAR32_AND_OR(0x400*i + addr[j] + MCHBAR32_AND_OR(0x400*i + 0x31c +
0xe + (k << 2), 0xe + (k << 2),
~0x3f3f3f3f, x32a[k]); ~0x3f3f3f3f, x32a[k]);
MCHBAR32_AND_OR(0x400*i + addr[j] + MCHBAR32_AND_OR(0x400*i + 0x31c +
0x2e + (k << 2), 0x2e + (k << 2),
~0x3f3f3f3f, x32a[k]); ~0x3f3f3f3f, x32a[k]);
} }
MCHBAR8_AND_OR(0x400*i + 0x31c, ~1, 0);
/* Now program the other RCOMP groups */
for (j = 0; j < 6; j++) {
if (j == 0) {
continue;
} else { } else {
MCHBAR16_AND_OR(0x400*i + addr[j], MCHBAR16_AND_OR(0x400*i + addr[j],
~0xf000, 0xa000); ~0xf000, 0xa000);
@ -1129,6 +1134,8 @@ static void prog_rcomp(struct sysinfo *s)
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a, MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a,
~0x3f3f3f3f, x39e[j]); ~0x3f3f3f3f, x39e[j]);
} }
/* Override command group strength multiplier */
if (s->spd_type == DDR3 && if (s->spd_type == DDR3 &&
BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
MCHBAR16_AND_OR(0x378 + 0x400 * i, MCHBAR16_AND_OR(0x378 + 0x400 * i,