arch/x86: Drop CBMEM_TOP_BACKUP
Code has evolved such that there seems to be little use for global definition of cbmem_top_chipset(). Even for AMD we had three different implementations. Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -133,12 +133,6 @@ config NUM_IPI_STARTS
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int
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default 2
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config CBMEM_TOP_BACKUP
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def_bool n
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help
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Platform implements non-volatile storage to cache cbmem_top()
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over stage transitions and optionally also over S3 suspend.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0xc00
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@ -164,7 +164,6 @@ romstage-y += post.c
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# gdt_init.S is included by entry32.inc when romstage is the first C
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# environment.
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romstage-y += gdt_init.S
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romstage-y += cbmem.c
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romstage-y += cpu_common.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
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romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
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@ -1,13 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#if CONFIG(CBMEM_TOP_BACKUP)
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void *cbmem_top_chipset(void)
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{
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/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
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return (void *)restore_top_of_low_cacheable();
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}
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#endif /* CBMEM_TOP_BACKUP */
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@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#include <amdblocks/biosram.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/cpu.h>
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@ -107,3 +107,9 @@ asmlinkage void car_stage_entry(void)
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{
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romstage_main();
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}
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void *cbmem_top_chipset(void)
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{
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/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
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return (void *)restore_top_of_low_cacheable();
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}
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@ -139,17 +139,6 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
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static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_;
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#endif /* ENV_RAMSTAGE */
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/* Any new chipset and board must implement cbmem_top() for both
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* romstage and ramstage to support early features like COLLECT_TIMESTAMPS
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* and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
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* value stored in nvram to enable early recovery on S3 path.
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*/
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#if ENV_X86
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void backup_top_of_low_cacheable(uintptr_t ramtop);
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uintptr_t restore_top_of_low_cacheable(void);
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#endif
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/*
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* Returns 0 for the stages where we know that cbmem does not come online.
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* Even if this function returns 1 for romstage, depending upon the point in
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@ -3,7 +3,6 @@
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config NORTHBRIDGE_AMD_AGESA
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bool
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default CPU_AMD_AGESA
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select CBMEM_TOP_BACKUP
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if NORTHBRIDGE_AMD_AGESA
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@ -2,8 +2,8 @@
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#include <Porting.h>
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#include <AGESA.h>
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#include <amdblocks/biosram.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <device/device.h>
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@ -1,9 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/biosram.h>
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#include <Porting.h>
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#include <AGESA.h>
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#include <cbmem.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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@ -1,9 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/biosram.h>
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#include <Porting.h>
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#include <AGESA.h>
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#include <cbmem.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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@ -1,9 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/biosram.h>
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#include "Porting.h"
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#include "AGESA.h"
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#include <cbmem.h>
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#include <device/device.h>
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#include <northbridge/amd/agesa/state_machine.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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@ -4,7 +4,6 @@ config NORTHBRIDGE_AMD_PI
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bool
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default y if CPU_AMD_PI
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default n
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select CBMEM_TOP_BACKUP
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if NORTHBRIDGE_AMD_PI
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@ -2,7 +2,6 @@
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/biosram.h>
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#include <cbmem.h>
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#include <device/mmio.h>
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#include <stdint.h>
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@ -5,6 +5,14 @@
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#include <stdint.h>
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/* Any new chipset and board must implement cbmem_top() for both
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* romstage and ramstage to support early features like COLLECT_TIMESTAMPS
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* and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top()
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* value stored in nvram to enable early recovery on S3 path.
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*/
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void backup_top_of_low_cacheable(uintptr_t ramtop);
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uintptr_t restore_top_of_low_cacheable(void);
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/* Returns the bootblock C entry point for APs */
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void *get_ap_entry_ptr(void);
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/* Used by BSP to store the bootblock entry point for APs */
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@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <timestamp.h>
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#include <amdblocks/biosram.h>
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@ -13,7 +13,7 @@
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#include <arch/bert_storage.h>
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#include <soc/northbridge.h>
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#include <soc/iomap.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/biosram.h>
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#if CONFIG(ACPI_BERT)
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#if CONFIG_SMM_TSEG_SIZE == 0x0
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