arch/x86: Drop CBMEM_TOP_BACKUP

Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.

Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-07-09 07:13:37 +03:00 committed by Nico Huber
parent bd5c721f6b
commit 2446c1e9e9
16 changed files with 23 additions and 43 deletions

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@ -133,12 +133,6 @@ config NUM_IPI_STARTS
int
default 2
config CBMEM_TOP_BACKUP
def_bool n
help
Platform implements non-volatile storage to cache cbmem_top()
over stage transitions and optionally also over S3 suspend.
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xc00

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@ -164,7 +164,6 @@ romstage-y += post.c
# gdt_init.S is included by entry32.inc when romstage is the first C
# environment.
romstage-y += gdt_init.S
romstage-y += cbmem.c
romstage-y += cpu_common.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S

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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
#if CONFIG(CBMEM_TOP_BACKUP)
void *cbmem_top_chipset(void)
{
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
return (void *)restore_top_of_low_cacheable();
}
#endif /* CBMEM_TOP_BACKUP */

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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
#include <amdblocks/biosram.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/cpu.h>

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@ -107,3 +107,9 @@ asmlinkage void car_stage_entry(void)
{
romstage_main();
}
void *cbmem_top_chipset(void)
{
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
return (void *)restore_top_of_low_cacheable();
}

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@ -139,17 +139,6 @@ void cbmem_add_records_to_cbtable(struct lb_header *header);
static cbmem_init_hook_t init_fn_ ## _unused3_ = init_fn_;
#endif /* ENV_RAMSTAGE */
/* Any new chipset and board must implement cbmem_top() for both
* romstage and ramstage to support early features like COLLECT_TIMESTAMPS
* and CBMEM_CONSOLE. Sometimes it is necessary to have cbmem_top()
* value stored in nvram to enable early recovery on S3 path.
*/
#if ENV_X86
void backup_top_of_low_cacheable(uintptr_t ramtop);
uintptr_t restore_top_of_low_cacheable(void);
#endif
/*
* Returns 0 for the stages where we know that cbmem does not come online.
* Even if this function returns 1 for romstage, depending upon the point in

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@ -3,7 +3,6 @@
config NORTHBRIDGE_AMD_AGESA
bool
default CPU_AMD_AGESA
select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_AGESA

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@ -2,8 +2,8 @@
#include <Porting.h>
#include <AGESA.h>
#include <amdblocks/biosram.h>
#include <arch/io.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <device/device.h>

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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/biosram.h>
#include <Porting.h>
#include <AGESA.h>
#include <cbmem.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>

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@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/biosram.h>
#include <Porting.h>
#include <AGESA.h>
#include <cbmem.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>

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@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/biosram.h>
#include "Porting.h"
#include "AGESA.h"
#include <cbmem.h>
#include <device/device.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>

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@ -4,7 +4,6 @@ config NORTHBRIDGE_AMD_PI
bool
default y if CPU_AMD_PI
default n
select CBMEM_TOP_BACKUP
if NORTHBRIDGE_AMD_PI

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@ -2,7 +2,6 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/biosram.h>
#include <cbmem.h>
#include <device/mmio.h>
#include <stdint.h>

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@ -5,6 +5,14 @@
#include <stdint.h>
/* Any new chipset and board must implement cbmem_top() for both
* romstage and ramstage to support early features like COLLECT_TIMESTAMPS
* and CBMEM_CONSOLE. With AMD it is necessary to have cbmem_top()
* value stored in nvram to enable early recovery on S3 path.
*/
void backup_top_of_low_cacheable(uintptr_t ramtop);
uintptr_t restore_top_of_low_cacheable(void);
/* Returns the bootblock C entry point for APs */
void *get_ap_entry_ptr(void);
/* Used by BSP to store the bootblock entry point for APs */

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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <cbmem.h>
#include <console/console.h>
#include <timestamp.h>
#include <amdblocks/biosram.h>

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@ -13,7 +13,7 @@
#include <arch/bert_storage.h>
#include <soc/northbridge.h>
#include <soc/iomap.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/biosram.h>
#if CONFIG(ACPI_BERT)
#if CONFIG_SMM_TSEG_SIZE == 0x0