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soc/intel/meteorlake: Remove space after a cast 

Change-Id: Ibf28fbdf791e7aa2faa41f3059150bf5ff5d21d1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77735
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2023-09-09 08:51:22 +02:00 committed by Felix Singer
parent 37833fc4be
commit 244a60ea44
2 changed files with 5 additions and 5 deletions
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8
src/soc/intel/meteorlake/crashlog.c
View File

@ -105,7 +105,7 @@ void cl_get_pmc_sram_data(void)
/* allocate memory for the PMC crash records to be copied */
unsigned long pmc_cl_cbmem_addr;
pmc_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_PMC_CRASHLOG,
pmc_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_PMC_CRASHLOG,
pmc_crashLog_size);
if (!pmc_cl_cbmem_addr) {
printk(BIOS_ERR, "Unable to allocate CBMEM PMC crashLog entry.\n");
@ -113,7 +113,7 @@ void cl_get_pmc_sram_data(void)
}
memset((void *)pmc_cl_cbmem_addr, 0, pmc_crashLog_size);
soc_pmc_dest = (u32 *)(uintptr_t) pmc_cl_cbmem_addr;
soc_pmc_dest = (u32 *)(uintptr_t)pmc_cl_cbmem_addr;
bool pmc_sram = true;
@ -179,7 +179,7 @@ void cl_get_pmc_sram_data(void)
/* allocate memory for the IOE crashlog records to be copied */
unsigned long ioe_cl_cbmem_addr;
ioe_cl_cbmem_addr = (unsigned long) cbmem_add(CBMEM_ID_IOE_CRASHLOG,
ioe_cl_cbmem_addr = (unsigned long)cbmem_add(CBMEM_ID_IOE_CRASHLOG,
ioe_crashLog_size);
if (!ioe_cl_cbmem_addr) {
printk(BIOS_ERR, "Unable to allocate CBMEM IOE crashLog entry.\n");
@ -187,7 +187,7 @@ void cl_get_pmc_sram_data(void)
}
memset((void *)ioe_cl_cbmem_addr, 0, ioe_crashLog_size);
ioe_pmc_dest = (u32 *)(uintptr_t) ioe_cl_cbmem_addr;
ioe_pmc_dest = (u32 *)(uintptr_t)ioe_cl_cbmem_addr;
/* process crashlog records for IOE SRAM */
for (int i = 0; i < descriptor_table.numb_regions + 1; i++) {

2
src/soc/intel/meteorlake/fsp_params.c
View File

@ -393,7 +393,7 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
* This would avoid APs from getting hijacked by FSP while coreboot
* decides to set SkipMpInit UPD.
*/
s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data();
/*
* Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature