GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/amd/phoenix: Add build rules to enable CBFS verification

Browse source 
Add SPI flash RO ranges to be verified by GSC in order to enable CBFS
verification. Also with CBFS verification enabled, CBFS metadata is
more than 64 bytes. So configure the offset of amdfw_a/b to 128 bytes -
next address aligned to 64 bytes.

BUG=b:277087492
TEST=Build and boot to OS in Myst with and without CBFS verification
enabled.

Change-Id: Ibfffd3d6fce8b80ec156a7b13b387e1df8c43347
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78233
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2023-10-04 17:42:37 -06:00 committed by Martin L Roth
parent 533efb2308
commit 244e3ffcbc
1 changed files with 15 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
src/soc/amd/phoenix/Makefile.inc
View file

@ -46,9 +46,9 @@ CPPFLAGS_common += -I$(src)/soc/amd/phoenix/acpi
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/phoenix
CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common
# 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# 0x80 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes
# Building the cbfs image will fail if the offset isn't large enough
AMD_FW_AB_POSITION := 0x40
AMD_FW_AB_POSITION := 0x80
PHOENIX_FW_A_POSITION=$(call int-add, \
$(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION))
@ -337,4 +337,17 @@ build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom
endif # CONFIG_SEPARATE_SIGNED_PSPFW
endif
# Add ranges for all components up until the first segment of BIOS to be verified by GSC
ifeq ($(CONFIG_VBOOT_GSCVD),y)
# Adding range for Bootblock
vboot-gscvd-ranges += $(call amdfwread-range-cmd,BIOSL2: 0x62)
# Adding range for PSP Stage1 Bootloader
vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x01)
ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
# Adding range for PSP Verstage
vboot-gscvd-ranges += $(call amdfwread-range-cmd,PSPL2: 0x52)
endif # ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
endif # ifeq ($(CONFIG_VBOOT_GSCVD),y)
endif # ($(CONFIG_SOC_AMD_PHOENIX),y)