diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 1e46ed025c..4536f31069 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -21,7 +21,9 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <bootblock_common.h>
+#include <console/console.h>
 #include <delay.h>
+#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>
@@ -55,6 +57,11 @@ void bootblock_mainboard_init(void)
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
 	rkclk_configure_cpu();
 
+	if (rkclk_was_watchdog_reset()) {
+		printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+		hard_reset();
+	}
+
 	/* i2c1 for tpm */
 	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
 
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 1e46ed025c..4536f31069 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -21,7 +21,9 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <bootblock_common.h>
+#include <console/console.h>
 #include <delay.h>
+#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>
@@ -55,6 +57,11 @@ void bootblock_mainboard_init(void)
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
 	rkclk_configure_cpu();
 
+	if (rkclk_was_watchdog_reset()) {
+		printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+		hard_reset();
+	}
+
 	/* i2c1 for tpm */
 	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
 
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 1e46ed025c..4536f31069 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -21,7 +21,9 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <bootblock_common.h>
+#include <console/console.h>
 #include <delay.h>
+#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>
@@ -55,6 +57,11 @@ void bootblock_mainboard_init(void)
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
 	rkclk_configure_cpu();
 
+	if (rkclk_was_watchdog_reset()) {
+		printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+		hard_reset();
+	}
+
 	/* i2c1 for tpm */
 	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
 
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 1e46ed025c..4536f31069 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -21,7 +21,9 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <bootblock_common.h>
+#include <console/console.h>
 #include <delay.h>
+#include <reset.h>
 #include <soc/clock.h>
 #include <soc/i2c.h>
 #include <soc/grf.h>
@@ -55,6 +57,11 @@ void bootblock_mainboard_init(void)
 	udelay(100);/* Must wait for voltage to stabilize,2mV/us */
 	rkclk_configure_cpu();
 
+	if (rkclk_was_watchdog_reset()) {
+		printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+		hard_reset();
+	}
+
 	/* i2c1 for tpm */
 	writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
 
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index fe42910dde..ab12e8c896 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -640,3 +640,9 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz)
 	}
 	return 0;
 }
+
+int rkclk_was_watchdog_reset(void)
+{
+	/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
+	return readl(&cru_ptr->cru_glb_rst_st) & 0x30;
+}
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index b8f892bbed..cbf4ba0df3 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -49,4 +49,5 @@ void rkclk_configure_tsadc(unsigned int hz);
 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
 int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
 void rkclk_configure_edp(void);
+int rkclk_was_watchdog_reset(void);
 #endif	/* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */