sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I2b1dc8befa3381f3edac06704e31e7ef50f86fa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27724 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Felix Held
parent
fe68a775d5
commit
2463aa9117
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@ -1947,17 +1947,15 @@ int write_training(ramctr_timing * ctrl)
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volatile u32 tmp;
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FOR_ALL_POPULATED_CHANNELS
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MCHBAR32(0x4008 + 0x400 * channel) =
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MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;
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MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000);
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FOR_ALL_POPULATED_CHANNELS {
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write_op(ctrl, channel);
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MCHBAR32(0x4020 + 0x400 * channel) =
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MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;
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MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000);
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}
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/* refresh disable */
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MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8;
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MCHBAR32_AND(0x5030, ~8);
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FOR_ALL_POPULATED_CHANNELS {
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write_op(ctrl, channel);
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}
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@ -1992,11 +1990,10 @@ int write_training(ramctr_timing * ctrl)
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wait_428c(channel);
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/* refresh enable */
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MCHBAR32(0x5030) = MCHBAR32(0x5030) | 8;
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MCHBAR32_OR(0x5030, 8);
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32(0x4020 + 0x400 * channel) =
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~0x00200000 & MCHBAR32(0x4020 + 0x400 * channel);
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MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x00200000);
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tmp = MCHBAR32(0x428c + 0x400 * channel);
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wait_428c(channel);
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@ -2171,12 +2168,11 @@ static void reprogram_320c(ramctr_timing * ctrl)
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MCHBAR32(0x4284 + 0x400 * channel) = 1;
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wait_428c(channel);
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MCHBAR32(0x4020 + 0x400 * channel) =
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MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;
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MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000);
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}
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/* refresh disable */
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MCHBAR32(0x5030) = MCHBAR32(0x5030) & ~8;
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MCHBAR32_AND(0x5030, ~8);
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FOR_ALL_POPULATED_CHANNELS {
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wait_428c(channel);
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@ -2353,8 +2349,7 @@ static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank,
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* in this mode only RD and RDA are allowed
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* all reads return a predefined pattern */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f000;
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MCHBAR32(0x4230 + 0x400 * channel) =
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0xc01 | (ctrl->tMOD << 16);
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MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tMOD << 16);
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | 0x360004;
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MCHBAR32(0x4210 + 0x400 * channel) = 0;
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@ -2803,10 +2798,8 @@ int discover_timC_write(ramctr_timing *ctrl)
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for (i = 0; i < 3; i++)
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32(0xe3c + (channel * 0x100)) =
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(rege3c_b24[i] << 24) |
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(MCHBAR32(0xe3c + (channel * 0x100))
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& ~0x3f000000);
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MCHBAR32_AND_OR(0xe3c + (channel * 0x100), ~0x3f000000,
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rege3c_b24[i] << 24);
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udelay(2);
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for (pat = 0; pat < NUM_PATTERNS; pat++) {
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FOR_ALL_POPULATED_RANKS {
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@ -2862,8 +2855,7 @@ int discover_timC_write(ramctr_timing *ctrl)
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}
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FOR_ALL_CHANNELS {
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MCHBAR32((channel * 0x100) + 0xe3c) =
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0 | (MCHBAR32((channel * 0x100) + 0xe3c) & ~0x3f000000);
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MCHBAR32_AND((channel * 0x100) + 0xe3c, ~0x3f000000);
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udelay(2);
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}
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@ -3060,10 +3052,8 @@ void set_4008c(ramctr_timing * ctrl)
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dram_odt_stretch(ctrl, channel);
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MCHBAR32(0x4008 + (channel << 10)) =
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0x0a000000
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| (b20 << 20)
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| ((ctrl->ref_card_offset[channel] + 2) << 16)
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| b4_8_12;
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0x0a000000 | (b20 << 20) |
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((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12;
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}
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}
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@ -3073,7 +3063,7 @@ void set_42a0(ramctr_timing * ctrl)
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FOR_ALL_POPULATED_CHANNELS {
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MCHBAR32(0x42a0 + 0x400 * channel) =
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0x00001000 | ctrl->rankmap[channel];
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MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
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MCHBAR32_AND(0x4004 + 0x400 * channel, ~0x20000000);
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}
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}
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@ -3094,8 +3084,8 @@ void final_registers(ramctr_timing * ctrl)
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MCHBAR32(0x4cd4) = 0x00000046;
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MCHBAR32(0x400c) = (MCHBAR32(0x400c) & 0xFFFFCFFF) | 0x1000; // OK
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MCHBAR32(0x440c) = (MCHBAR32(0x440c) & 0xFFFFCFFF) | 0x1000; // OK
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MCHBAR32_AND_OR(0x400c, 0xFFFFCFFF, 0x1000);
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MCHBAR32_AND_OR(0x440c, 0xFFFFCFFF, 0x1000);
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if (is_mobile)
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/* APD - DLL Off, 64 DCLKs until idle, decision per rank */
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@ -3129,14 +3119,14 @@ void final_registers(ramctr_timing * ctrl)
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}
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MCHBAR32(0x5880) = 0xca9171e5;
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MCHBAR32(0x5888) = (MCHBAR32(0x5888) & ~0xffffff) | 0xe4d5d0;
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MCHBAR32(0x58a8) = MCHBAR32(0x58a8) & ~0x1f;
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MCHBAR32(0x4294) = (MCHBAR32(0x4294) & ~0x30000) | (1 << 16);
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MCHBAR32(0x4694) = (MCHBAR32(0x4694) & ~0x30000) | (1 << 16);
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MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0);
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MCHBAR32_AND(0x58a8, ~0x1f);
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MCHBAR32_AND_OR(0x4294, ~0x30000, 1 << 16);
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MCHBAR32_AND_OR(0x4694, ~0x30000, 1 << 16);
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MCHBAR32(0x5030) |= 1; // OK
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MCHBAR32(0x5030) |= 0x80; // OK
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MCHBAR32(0x5f18) = 0xfa; // OK
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MCHBAR32(0x5030) |= 1;
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MCHBAR32(0x5030) |= 0x80;
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MCHBAR32(0x5f18) = 0xfa;
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/* Find a populated channel. */
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FOR_ALL_POPULATED_CHANNELS
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@ -3194,13 +3184,11 @@ void restore_timings(ramctr_timing * ctrl)
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}
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FOR_ALL_POPULATED_CHANNELS
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MCHBAR32(0x4008 + 0x400 * channel) =
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MCHBAR32(0x4008 + 0x400 * channel) | 0x8000000;
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MCHBAR32_OR(0x4008 + 0x400 * channel, 0x8000000);
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FOR_ALL_POPULATED_CHANNELS {
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udelay (1);
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MCHBAR32(0x4020 + 0x400 * channel) =
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MCHBAR32(0x4020 + 0x400 * channel) | 0x200000;
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MCHBAR32_OR(0x4020 + 0x400 * channel, 0x200000);
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}
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printram("CPE\n");
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@ -3253,8 +3241,7 @@ void restore_timings(ramctr_timing * ctrl)
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MCHBAR32(0x3000) = 0;
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FOR_ALL_CHANNELS {
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MCHBAR32(channel * 0x100 + 0xe3c) =
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0 | (MCHBAR32(channel * 0x100 + 0xe3c) & ~0x3f000000);
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MCHBAR32_AND(channel * 0x100 + 0xe3c, ~0x3f000000);
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udelay(2);
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}
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