soc/intel/mtl/acpi/xhci: Add clock gating support

Implement PS0 and PS3 methods to support xHCI clock gating in S0ix
suspend and resume.

BUG=b:283989367
TEST=S0iX test passed

Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/meteorlake/acpi/xhci.asl

@@ -16,12 +16,14 @@ Device (XHCI)
 
 	Method (_PS0, 0, Serialized)
 	{
-
+		/* Disable Clock Gating */
+		^^PCRA (PID_XHCI, 0x0,  ~(1 << 3))
 	}
 
 	Method (_PS3, 0, Serialized)
 	{
-
+		/* Enable Clock Gating */
+		^^PCRO (PID_XHCI, 0x0, 1 << 3)
 	}
 
 	/* Root Hub for Meteorlake */

src/soc/intel/meteorlake/include/soc/pcr_ids.h

@@ -28,5 +28,6 @@
 #define PID_ISCLK	0x64
 #define PID_DMI		0x88
 #define PID_IOM		0xAA
+#define PID_XHCI	0x3A
 
 #endif