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mb/amd/majolica: Add eSPI support 

Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Zheng Bao 2021-01-27 15:48:35 +08:00 committed by Felix Held
parent b2f3151ed9
commit 2494aa952c
2 changed files with 13 additions and 0 deletions
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1
src/mainboard/amd/majolica/Kconfig
View File

@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select SOC_AMD_CEZANNE select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI
select AMD_SOC_CONSOLE_UART select AMD_SOC_CONSOLE_UART
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS

12
src/mainboard/amd/majolica/devicetree.cb
View File

@ -1,6 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
chip soc/amd/cezanne chip soc/amd/cezanne
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN,
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 1,
.flash_ch_en = 0,
}"
device domain 0 on device domain 0 on
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A