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mb/google/rex: Avoid LPDDR5/x hang 

This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.

As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.

BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2023-06-23 19:40:14 +05:30
parent 80254118ac
commit 249aede238
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
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@ -41,7 +41,7 @@ chip soc/intel/meteorlake
register "sagv" = "SAGV_ENABLED"
register "sagv_freq_mhz[0]" = "2133"
register "sagv_freq_mhz[0]" = "3200"
register "sagv_gear[0]" = "4"
register "sagv_freq_mhz[1]" = "6000"