nb/intel/sandybridge/raminit: prepare raminit for fallback
Return errors to top level ram init function. Required by the folowing series to implement a fallback. No functionality is changed. On error case the system still halts in every test. Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph
Martin Roth
parent
101351fe95
commit
24a845b622
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@ -199,6 +199,8 @@ typedef struct ramctr_timing_st {
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#define MAX_TIMB 511
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#define MAX_TIMA 127
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#define MAKE_ERR ((channel<<16)|(slotrank<<8)|1)
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static void program_timings(ramctr_timing * ctrl, int channel);
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static const char *ecc_decoder[] = {
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@ -1877,7 +1879,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank,
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}
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}
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static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank,
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static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank,
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int *upperA)
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{
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int works[NUM_LANES];
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@ -1895,18 +1897,26 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank,
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all_works = 0;
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}
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if (all_works)
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return;
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return 0;
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if (!some_works) {
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if (ctrl->timings[channel][slotrank].val_4024 < 2)
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die("402x discovery failed");
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if (ctrl->timings[channel][slotrank].val_4024 < 2) {
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printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n",
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channel, slotrank);
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halt();
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return MAKE_ERR;
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}
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ctrl->timings[channel][slotrank].val_4024 -= 2;
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printram("4024 -= 2;\n");
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continue;
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}
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ctrl->timings[channel][slotrank].val_4028 += 2;
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printram("4028 += 2;\n");
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if (ctrl->timings[channel][slotrank].val_4028 >= 0x10)
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die("402x discovery failed");
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if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) {
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printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n",
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channel, slotrank);
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halt();
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return MAKE_ERR;
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}
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FOR_ALL_LANES if (works[lane]) {
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ctrl->timings[channel][slotrank].lanes[lane].timA +=
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128;
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@ -1915,6 +1925,7 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank,
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slotrank, lane);
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}
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}
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return 0;
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}
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struct timA_minmax {
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@ -1983,9 +1994,10 @@ static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank,
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* Once the controller has detected this pattern a bit in the result register is
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* set for the current phase shift.
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*/
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static void read_training(ramctr_timing * ctrl)
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static int read_training(ramctr_timing * ctrl)
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{
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int channel, slotrank, lane;
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int err;
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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int all_high, some_high;
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@ -2041,7 +2053,9 @@ static void read_training(ramctr_timing * ctrl)
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pre_timA_change(ctrl, channel, slotrank, &mnmx);
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discover_402x(ctrl, channel, slotrank, upperA);
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err = discover_402x(ctrl, channel, slotrank, upperA);
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if (err)
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return err;
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post_timA_change(ctrl, channel, slotrank, &mnmx);
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pre_timA_change(ctrl, channel, slotrank, &mnmx);
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@ -2081,6 +2095,7 @@ static void read_training(ramctr_timing * ctrl)
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write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel
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+ 4 * lane, 0);
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}
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return 0;
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}
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static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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@ -2167,7 +2182,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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wait_428c(channel);
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}
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static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
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static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)
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{
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int timC;
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int statistics[NUM_LANES][MAX_TIMC + 1];
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@ -2204,11 +2219,16 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank)
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struct run rn =
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get_longest_zero_run(statistics[lane], MAX_TIMC + 1);
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ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle;
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if (rn.all)
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die("timC discovery failed");
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if (rn.all) {
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printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n",
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channel, slotrank, lane);
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halt();
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return MAKE_ERR;
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}
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printram("Cval: %d, %d, %d: %x\n", channel, slotrank,
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lane, ctrl->timings[channel][slotrank].lanes[lane].timC);
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}
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return 0;
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}
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static int get_precedening_channels(ramctr_timing * ctrl, int target_channel)
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@ -2402,7 +2422,7 @@ static void test_timB(ramctr_timing * ctrl, int channel, int slotrank)
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0x1080 | make_mr1(ctrl, slotrank, channel));
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}
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static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
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static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
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{
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int timB;
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int statistics[NUM_LANES][128];
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@ -2445,11 +2465,16 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
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else if ((rn.start & 0x3F) == 0x3F)
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rn.start += 1;
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ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
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if (rn.all)
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die("timB discovery failed");
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if (rn.all) {
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printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n",
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channel, slotrank, lane);
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halt();
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return MAKE_ERR;
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}
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printram("Bval: %d, %d, %d: %x\n", channel, slotrank,
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lane, ctrl->timings[channel][slotrank].lanes[lane].timB);
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}
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return 0;
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}
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static int get_timB_high_adjust(u64 val)
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@ -2606,9 +2631,10 @@ static void write_op(ramctr_timing * ctrl, int channel)
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* In this mode the DRAM-chip samples the CLK on every DQS edge and feeds back the
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* sampled value on the data lanes (DQs).
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*/
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static void write_training(ramctr_timing * ctrl)
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static int write_training(ramctr_timing * ctrl)
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{
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int channel, slotrank, lane;
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int err;
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FOR_ALL_POPULATED_CHANNELS
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write32(DEFAULT_MCHBAR + 0x4008 + 0x400 * channel,
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@ -2641,8 +2667,11 @@ static void write_training(ramctr_timing * ctrl)
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toggle_io_reset();
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/* set any valid value for timB, it gets corrected later */
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
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discover_timB(ctrl, channel, slotrank);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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err = discover_timB(ctrl, channel, slotrank);
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if (err)
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return err;
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}
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/* disable write leveling on all ranks */
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
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@ -2691,8 +2720,11 @@ static void write_training(ramctr_timing * ctrl)
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write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
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}
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
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discover_timC(ctrl, channel, slotrank);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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err = discover_timC(ctrl, channel, slotrank);
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if (err)
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return err;
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}
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FOR_ALL_POPULATED_CHANNELS
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program_timings(ctrl, channel);
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@ -2708,6 +2740,7 @@ static void write_training(ramctr_timing * ctrl)
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write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
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0);
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}
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return 0;
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}
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static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
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@ -2876,7 +2909,7 @@ static void reprogram_320c(ramctr_timing * ctrl)
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#define MIN_C320C_LEN 13
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static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch)
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static int try_cmd_stretch(ramctr_timing *ctrl, int cmd_stretch)
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{
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struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS];
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int channel, slotrank;
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@ -2941,19 +2974,20 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch)
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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ctrl->timings[channel][slotrank] = saved_timings[channel][slotrank];
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}
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return 0;
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return MAKE_ERR;
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}
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}
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}
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return 1;
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return 0;
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}
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/* Adjust CMD phase shift and try multiple command rates.
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* A command rate of 2T doubles the time needed for address and
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* command decode. */
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static void command_training(ramctr_timing * ctrl)
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static int command_training(ramctr_timing *ctrl)
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{
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int channel;
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int err;
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FOR_ALL_POPULATED_CHANNELS {
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fill_pattern5(ctrl, channel, 0);
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@ -2961,17 +2995,25 @@ static void command_training(ramctr_timing * ctrl)
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}
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/* try command rate 1T and 2T */
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if (!try_cmd_stretch(ctrl, 0) && !try_cmd_stretch(ctrl, 2))
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die("c320c discovery failed");
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err = try_cmd_stretch(ctrl, 0);
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if (err) {
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err = try_cmd_stretch(ctrl, 2);
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if (err) {
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printk(BIOS_EMERG, "c320c discovery failed\n");
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halt();
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return err;
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}
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}
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FOR_ALL_POPULATED_CHANNELS {
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program_timings(ctrl, channel);
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}
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reprogram_320c(ctrl);
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return 0;
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}
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static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank,
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static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank,
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int *edges)
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{
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int edge;
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@ -3044,18 +3086,24 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank,
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struct run rn =
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get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1);
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edges[lane] = rn.middle;
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if (rn.all)
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die("edge discovery failed");
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if (rn.all) {
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printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n",
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channel, slotrank, lane);
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halt();
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return MAKE_ERR;
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}
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printram("eval %d, %d, %d: %02x\n", channel, slotrank,
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lane, edges[lane]);
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}
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return 0;
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}
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static void discover_edges(ramctr_timing * ctrl)
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static int discover_edges(ramctr_timing *ctrl)
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{
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int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int channel, slotrank, lane;
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int err;
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write32(DEFAULT_MCHBAR + 0x3400, 0);
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@ -3210,16 +3258,20 @@ static void discover_edges(ramctr_timing * ctrl)
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printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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discover_edges_real(ctrl, channel, slotrank,
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err = discover_edges_real(ctrl, channel, slotrank,
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falling_edges[channel][slotrank]);
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if (err)
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return err;
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}
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write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
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printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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discover_edges_real(ctrl, channel, slotrank,
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err = discover_edges_real(ctrl, channel, slotrank,
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rising_edges[channel][slotrank]);
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if (err)
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return err;
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}
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write32(DEFAULT_MCHBAR + 0x4eb0, 0);
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@ -3239,9 +3291,10 @@ static void discover_edges(ramctr_timing * ctrl)
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write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
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0);
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}
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return 0;
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}
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static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
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static int discover_edges_write_real(ramctr_timing *ctrl, int channel,
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int slotrank, int *edges)
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{
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int edge;
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@ -3353,38 +3406,47 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel,
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upper[lane] =
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min(rn.end - ctrl->edge_offset[i], upper[lane]);
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edges[lane] = (lower[lane] + upper[lane]) / 2;
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if (rn.all || (lower[lane] > upper[lane]))
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die("edge write discovery failed");
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if (rn.all || (lower[lane] > upper[lane])) {
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printk(BIOS_EMERG, "edge write discovery failed: %d, %d, %d\n",
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channel, slotrank, lane);
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halt();
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return MAKE_ERR;
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}
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}
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}
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}
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write32(DEFAULT_MCHBAR + 0x3000, 0);
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printram("CPA\n");
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return 0;
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}
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static void discover_edges_write(ramctr_timing * ctrl)
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static int discover_edges_write(ramctr_timing *ctrl)
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{
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int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
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int channel, slotrank, lane;
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int err;
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/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
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write32(DEFAULT_MCHBAR + 0x4eb0, 0x300);
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printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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discover_edges_write_real(ctrl, channel, slotrank,
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err = discover_edges_write_real(ctrl, channel, slotrank,
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falling_edges[channel][slotrank]);
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if (err)
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return err;
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}
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write32(DEFAULT_MCHBAR + 0x4eb0, 0x200);
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printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200);
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FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
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discover_edges_write_real(ctrl, channel, slotrank,
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err = discover_edges_write_real(ctrl, channel, slotrank,
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rising_edges[channel][slotrank]);
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if (err)
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return err;
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}
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write32(DEFAULT_MCHBAR + 0x4eb0, 0);
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@ -3403,6 +3465,7 @@ static void discover_edges_write(ramctr_timing * ctrl)
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write32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane,
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0);
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}
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return 0;
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}
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static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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@ -3455,7 +3518,7 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank)
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wait_428c(channel);
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}
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static void discover_timC_write(ramctr_timing * ctrl)
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static int discover_timC_write(ramctr_timing *ctrl)
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{
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const u8 rege3c_b24[3] = { 0, 0xf, 0x2f };
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int i, pat;
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@ -3509,8 +3572,12 @@ static void discover_timC_write(ramctr_timing * ctrl)
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rn = get_longest_zero_run(statistics,
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MAX_TIMC + 1);
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if (rn.all)
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die("timC write discovery failed");
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if (rn.all) {
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printk(BIOS_EMERG, "timC write discovery failed: %d, %d, %d\n",
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channel, slotrank, lane);
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halt();
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return MAKE_ERR;
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}
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printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n",
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channel, slotrank, i, rn.start,
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rn.middle, rn.end,
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@ -3551,6 +3618,7 @@ static void discover_timC_write(ramctr_timing * ctrl)
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FOR_ALL_POPULATED_CHANNELS {
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program_timings(ctrl, channel);
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}
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return 0;
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}
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static void normalize_training(ramctr_timing * ctrl)
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@ -3585,13 +3653,18 @@ static void write_controller_mr(ramctr_timing * ctrl)
|
|||
}
|
||||
}
|
||||
|
||||
static void channel_test(ramctr_timing * ctrl)
|
||||
static int channel_test(ramctr_timing *ctrl)
|
||||
{
|
||||
int channel, slotrank, lane;
|
||||
|
||||
slotrank = 0;
|
||||
FOR_ALL_POPULATED_CHANNELS
|
||||
if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000)
|
||||
die("Mini channel test failed (1)\n");
|
||||
if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) {
|
||||
printk(BIOS_EMERG, "Mini channel test failed (1): %d\n",
|
||||
channel);
|
||||
halt();
|
||||
return MAKE_ERR;
|
||||
}
|
||||
FOR_ALL_POPULATED_CHANNELS {
|
||||
fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
|
||||
|
||||
|
|
@ -3633,9 +3706,14 @@ static void channel_test(ramctr_timing * ctrl)
|
|||
write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001);
|
||||
wait_428c(channel);
|
||||
FOR_ALL_LANES
|
||||
if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane))
|
||||
die("Mini channel test failed (2)\n");
|
||||
if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) {
|
||||
printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n",
|
||||
channel, slotrank, lane);
|
||||
halt();
|
||||
return MAKE_ERR;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void set_scrambling_seed(ramctr_timing * ctrl)
|
||||
|
|
@ -3949,6 +4027,8 @@ static void restore_timings(ramctr_timing * ctrl)
|
|||
static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume,
|
||||
int me_uma_size)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (!s3resume) {
|
||||
/* Find fastest common supported parameters */
|
||||
dram_find_common_params(ctrl);
|
||||
|
|
@ -4016,22 +4096,35 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume,
|
|||
/* Prepare for memory training */
|
||||
prepare_training(ctrl);
|
||||
|
||||
read_training(ctrl);
|
||||
write_training(ctrl);
|
||||
err = read_training(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = write_training(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
printram("CP5a\n");
|
||||
|
||||
discover_edges(ctrl);
|
||||
err = discover_edges(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
printram("CP5b\n");
|
||||
|
||||
command_training(ctrl);
|
||||
err = command_training(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
printram("CP5c\n");
|
||||
|
||||
discover_edges_write(ctrl);
|
||||
err = discover_edges_write(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
discover_timC_write(ctrl);
|
||||
err = discover_timC_write(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
normalize_training(ctrl);
|
||||
}
|
||||
|
|
@ -4041,7 +4134,9 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int s3resume,
|
|||
write_controller_mr(ctrl);
|
||||
|
||||
if (!s3resume) {
|
||||
channel_test(ctrl);
|
||||
err = channel_test(ctrl);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue