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soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T 

It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.

FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.

Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.

Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN

Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-11-25 11:57:28 +05:30
parent 0d2dbcab5f
commit 24ab1c5db6
7 changed files with 50 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/Makefile.inc
View File

@ -59,9 +59,4 @@ $(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
cpu_microcode_blob.bin-type := microcode
ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
else
cpu_microcode_blob.bin-align := 16
endif

15
src/drivers/intel/fsp2_0/Kconfig
View File

@ -37,21 +37,6 @@ config ADD_FSP_BINARIES
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
use the FSP-T binary and it is not added.
config CPU_MICROCODE_CBFS_LEN
hex "Microcode update region length in bytes"
depends on FSP_CAR
default 0x0
help
The length in bytes of the microcode update region.
config CPU_MICROCODE_CBFS_LOC
hex "Microcode update base address in CBFS"
depends on FSP_CAR
default 0x0
help
The location (base address) in CBFS that contains the
microcode update binary.
config FSP_T_CBFS
string "Name of FSP-T in CBFS"
depends on FSP_CAR

11
src/soc/intel/apollolake/fspcar.c
View File

@ -25,6 +25,17 @@ const FSPT_UPD temp_ram_init_params = {
.FsptCommonUpd = {
.Revision = 0,
.Reserved = {0},
/*
* It is a requirement for firmware to have Firmware Interface Table
* (FIT), which contains pointers to each microcode update.
* The microcode update is loaded for all logical processors before
* cpu reset vector.
*
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =

17
src/soc/intel/cannonlake/bootblock/bootblock.c
View File

@ -30,10 +30,19 @@ const FSPT_UPD temp_ram_init_params = {
.Reserved = {0},
},
.FsptCoreUpd = {
.MicrocodeRegionBase =
(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
.MicrocodeRegionSize =
(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
/*
* It is a requirement for firmware to have Firmware Interface Table
* (FIT), which contains pointers to each microcode update.
* The microcode update is loaded for all logical processors before
* cpu reset vector.
*
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,

8
src/soc/intel/denverton_ns/Kconfig
View File

@ -108,14 +108,6 @@ config DCACHE_BSP_STACK_SIZE
hex
default 0x10000
config CPU_MICROCODE_CBFS_LOC
hex
default 0xfff20040
config CPU_MICROCODE_CBFS_LEN
hex
default 0x0ff80
config CPU_BCLK_MHZ
int
default 100

17
src/soc/intel/denverton_ns/bootblock/bootblock.c
View File

@ -31,10 +31,19 @@ const FSPT_UPD temp_ram_init_params = {
.Reserved = {0},
},
.FsptCoreUpd = {
.MicrocodeRegionBase =
(UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
.MicrocodeRegionLength =
(UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
/*
* It is a requirement for firmware to have Firmware Interface Table
* (FIT), which contains pointers to each microcode update.
* The microcode update is loaded for all logical processors before
* cpu reset vector.
*
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =
(UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,

17
src/soc/intel/skylake/fspcar.c
View File

@ -23,10 +23,19 @@ const FSPT_UPD temp_ram_init_params = {
.Reserved = {0},
},
.FsptCoreUpd = {
.MicrocodeRegionBase =
(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
.MicrocodeRegionSize =
(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
/*
* It is a requirement for firmware to have Firmware Interface Table
* (FIT), which contains pointers to each microcode update.
* The microcode update is loaded for all logical processors before
* cpu reset vector.
*
* All SoC since Gen-4 has above mechanism in place to load microcode
* even before hitting CPU reset vector. Hence skipping FSP-T loading
* microcode after CPU reset by passing '0' value to
* FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
*/
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,