From 24ae31cdc6940320bd0a5cccf2d991b2fd31e236 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Sat, 17 Apr 2021 13:45:00 -0700 Subject: [PATCH] soc/intel/alderlake: Fix devices list in the DMAR DRHD structure The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/acpi.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index db005e8bcf..664c40ba3d 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -198,6 +198,23 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } + /* TCSS Thunderbolt root ports */ + for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { + const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (is_dev_enabled(tbt_dev)) { + const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; + const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; + if (tbtbar && tbten) { + const unsigned long tmp = current; + + current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); + + acpi_dmar_drhd_fixup(tmp, current); + } + } + } + const uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; const bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; @@ -216,23 +233,6 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - /* TCSS Thunderbolt root ports */ - for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) { - const struct device *const tbt_dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); - if (is_dev_enabled(tbt_dev)) { - const uint64_t tbtbar = MCHBAR64(TBTxBAR(i)) & VTBAR_MASK; - const bool tbten = MCHBAR32(TBTxBAR(i)) & VTBAR_ENABLED; - if (tbtbar && tbten) { - const unsigned long tmp = current; - - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); - current += acpi_create_dmar_ds_pci_br(current, 0, 7, i); - - acpi_dmar_drhd_fixup(tmp, current); - } - } - } - /* Add RMRR entry */ if (is_dev_enabled(igfx_dev)) { const unsigned long tmp = current;