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soc/intel/alderlake: Set SaIpuEnable UPD according to devicetree 

The SaIpuEnable UPD is not currently being touched by coreboot; set it
according to the enabled status of the corresponding devicetree node.

TEST=turn ipu device on or off in devicetree, see device enumerated or
not in OS, according to the devicetree setting.

Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-06-02 13:08:15 -06:00
parent 3102fd0f8f
commit 24b1c54226
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/alderlake/romstage/fsp_params.c
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@ -207,6 +207,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(SA_DEVFN_TBT3); dev = pcidev_path_on_root(SA_DEVFN_TBT3);
m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
/* IPU */
dev = pcidev_path_on_root(SA_DEVFN_IPU);
m_cfg->SaIpuEnable = is_dev_enabled(dev);
/* VT-d config */ /* VT-d config */
m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS;
m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;