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nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors 

Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.

Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-01-20 12:00:31 +01:00 committed by Patrick Georgi
parent a8df6cff16
commit 24b1d8af06
5 changed files with 19 additions and 38 deletions
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9
src/northbridge/intel/pineview/Kconfig
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@ -31,4 +31,13 @@ config SMM_RESERVED_SIZE
hex hex
default 0x80000 default 0x80000
config FIXED_MCHBAR_MMIO_BASE
default 0xfed14000
config FIXED_DMIBAR_MMIO_BASE
default 0xfed18000
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
endif endif

7
src/northbridge/intel/pineview/acpi/pineview.asl
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@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../memmap.h"
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */
Device (PDRC) Device (PDRC)
@ -13,9 +12,9 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() { Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */

6
src/northbridge/intel/pineview/early_init.c
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@ -136,9 +136,9 @@ static void pineview_setup_bars(void)
pci_write_config8(HOST_BRIDGE, 0x08, 0x69); pci_write_config8(HOST_BRIDGE, 0x08, 0x69);
/* Set up all hardcoded northbridge BARs */ /* Set up all hardcoded northbridge BARs */
pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1); pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1);
/* Set C0000-FFFFF to access RAM on both reads and writes */ /* Set C0000-FFFFF to access RAM on both reads and writes */

11
src/northbridge/intel/pineview/memmap.h
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef PINEVIEW_MEMMAP_H
#define PINEVIEW_MEMMAP_H
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_PMIOBAR 0x00000400
#endif /* PINEVIEW_MEMMAP_H */

24
src/northbridge/intel/pineview/pineview.h
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@ -3,9 +3,10 @@
#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
#define NORTHBRIDGE_INTEL_PINEVIEW_H #define NORTHBRIDGE_INTEL_PINEVIEW_H
#include <northbridge/intel/pineview/memmap.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#define DEFAULT_PMIOBAR 0x00000400
#define BOOT_PATH_NORMAL 0 #define BOOT_PATH_NORMAL 0
#define BOOT_PATH_RESET 1 #define BOOT_PATH_RESET 1
#define BOOT_PATH_RESUME 2 #define BOOT_PATH_RESUME 2
@ -32,9 +33,8 @@
* MCHBAR * MCHBAR
*/ */
#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #include <northbridge/intel/common/fixed_bars.h>
#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and))
#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and))
#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and))
@ -49,22 +49,6 @@
#include "mchbar_regs.h" #include "mchbar_regs.h"
/*
* EPBAR - Egress Port Root Complex Register Block
*/
#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x))))
#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x))))
#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
/*
* DMIBAR
*/
#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
void pineview_early_init(void); void pineview_early_init(void);
u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_memory_size(const u32 gms);
u32 decode_igd_gtt_size(const u32 gsm); u32 decode_igd_gtt_size(const u32 gsm);