GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

gizmosphere/gizmo2: Switch away from ROMCC_BOOTBLOCK 

Warning: Not tested on hardware.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Iad86755952204bb1a56ef341e626b0627a958467
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38868
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mike Banon 2020-02-13 15:39:42 +00:00 committed by Patrick Georgi
parent 541498be0a
commit 24c1f94258
5 changed files with 35 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/gizmosphere/gizmo2/Kconfig
View File

@ -14,14 +14,10 @@
# GNU General Public License for more details.
#
config BOARD_GIZMOSPHERE_GIZMO2
def_bool n
if BOARD_GIZMOSPHERE_GIZMO2
config BOARD_SPECIFIC_OPTIONS
def_bool y
#select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY16_KB
select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
select SOUTHBRIDGE_AMD_AGESA_YANGTZE

4
src/mainboard/gizmosphere/gizmo2/Kconfig.name
View File

@ -1,2 +1,2 @@
#config BOARD_GIZMOSPHERE_GIZMO2
# bool"Gizmo2"
config BOARD_GIZMOSPHERE_GIZMO2
bool "Gizmo2"

2
src/mainboard/gizmosphere/gizmo2/Makefile.inc
View File

@ -14,6 +14,8 @@
# GNU General Public License for more details.
#
bootblock-y += bootblock.c
romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c

31
src/mainboard/gizmosphere/gizmo2/bootblock.c Normal file
View File

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <amdblocks/acpimmio.h>
#include <bootblock_common.h>
void bootblock_mainboard_early_init(void)
{
#if 0
volatile u32 i, val;
/* LPC clock? Should happen before enable_serial. */
/*
* On Larne, after LpcClkDrvSth is set, it needs some time to be stable,
* because of the buffer ICS551M
*/
for (i = 0; i < 200000; i++)
val = inb(0xcd6);
#endif
}

34
src/mainboard/gizmosphere/gizmo2/romstage.c
View File

@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <amdblocks/acpimmio.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
void board_BeforeAgesa(struct sysinfo *cb)
{
/* For serial port option, plug-in card on LPC. */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
* LpcClk[1:0]". To be consistent with Parmer, setting to 4mA
* even though the register is not documented in the Kabini BKDG.
* Otherwise the serial output is bad code.
*/
pm_io_write8(0xd2, 0);
}