- See Issue Tracker id-8 "lnxi-patch-8".
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jason Schildt
parent
00e463f730
commit
24ca17e3ea
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@ -3,6 +3,60 @@
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include <arch/io.h>
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_BIOSR_Detect (1<<5)
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/* If we assume a symmetric processor configuration we can
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* get all of the information we need to write the processor
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* entry from the bootstrap processor.
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* Plus I don't think linux really even cares.
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* Having the proper apicid's in the table so the non-bootstrap
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* processors can be woken up should be enough. Linux-2.6.11 work-around.
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*/
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void smp_write_processors_inorder(struct mp_config_table *mc)
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{
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int boot_apic_id;
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int order_id;
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unsigned apic_version;
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unsigned cpu_features;
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unsigned cpu_feature_flags;
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struct cpuid_result result;
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device_t cpu;
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boot_apic_id = lapicid();
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apic_version = lapic_read(LAPIC_LVR) & 0xff;
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result = cpuid(1);
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cpu_features = result.eax;
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cpu_feature_flags = result.edx;
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/* order the output of the cpus to fix a bug in kernel 6 11 */
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for(order_id = 0;order_id <256; order_id++) {
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for(cpu = all_devices; cpu; cpu = cpu->next) {
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unsigned long cpu_flag;
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if ((cpu->path.type != DEVICE_PATH_APIC) ||
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(cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
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{
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continue;
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}
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if (!cpu->enabled) {
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continue;
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}
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cpu_flag = MPC_CPU_ENABLED;
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if (boot_apic_id == cpu->path.u.apic.apic_id) {
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cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
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}
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if(cpu->path.u.apic.apic_id == order_id) {
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smp_write_processor(mc,
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cpu->path.u.apic.apic_id, apic_version,
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cpu_flag, cpu_features, cpu_feature_flags);
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break;
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}
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}
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}
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}
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static unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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@ -38,6 +92,21 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
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return 0;
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}
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unsigned max_apicid(void)
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{
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unsigned max_apicid;
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device_t dev;
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max_apicid = 0;
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for(dev = all_devices; dev; dev = dev->next) {
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if (dev->path.type != DEVICE_PATH_APIC)
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continue;
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if (dev->path.u.apic.apic_id > max_apicid) {
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max_apicid = dev->path.u.apic.apic_id;
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}
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}
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return max_apicid;
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}
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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@ -50,6 +119,10 @@ void *smp_write_config_table(void *v)
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unsigned char bus_8131_1;
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unsigned char bus_8131_2;
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unsigned char bus_8111_1;
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unsigned apicid_base;
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unsigned apicid_8111;
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unsigned apicid_8131_1;
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unsigned apicid_8131_2;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -68,8 +141,12 @@ void *smp_write_config_table(void *v)
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc);
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smp_write_processors_inorder(mc);
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apicid_base = max_apicid() + 1;
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apicid_8111 = apicid_base;
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apicid_8131_1 = apicid_base + 1;
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apicid_8131_2 = apicid_base + 2;
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{
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device_t dev;
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@ -124,7 +201,7 @@ void *smp_write_config_table(void *v)
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smp_write_bus(mc, bus_isa, "ISA ");
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/* IOAPIC handling */
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
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{
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device_t dev;
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struct resource *res;
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@ -133,7 +210,7 @@ void *smp_write_config_table(void *v)
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x03, 0x11, res->base);
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smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
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}
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}
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/* 8131 apic 4 */
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@ -141,44 +218,44 @@ void *smp_write_config_table(void *v)
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, 0x04, 0x11, res->base);
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smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
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}
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}
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}
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/* ISA backward compatibility interrupts */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x00);
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bus_isa, 0x00, apicid_8111, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x02, 0x01);
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bus_isa, 0x01, apicid_8111, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x02);
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bus_isa, 0x00, apicid_8111, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x02, 0x03);
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bus_isa, 0x03, apicid_8111, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x02, 0x04);
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bus_isa, 0x04, apicid_8111, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x05, 0x02, 0x05);
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bus_isa, 0x05, apicid_8111, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x02, 0x06);
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bus_isa, 0x06, apicid_8111, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x07, 0x02, 0x07);
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bus_isa, 0x07, apicid_8111, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x08, 0x02, 0x08);
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bus_isa, 0x08, apicid_8111, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x02, 0x09);
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bus_isa, 0x09, apicid_8111, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0a, 0x02, 0x0a);
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bus_isa, 0x0a, apicid_8111, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0b, 0x02, 0x0b);
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bus_isa, 0x0b, apicid_8111, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x02, 0x0c);
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bus_isa, 0x0c, apicid_8111, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x02, 0x0d);
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bus_isa, 0x0d, apicid_8111, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x02, 0x0e);
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bus_isa, 0x0e, apicid_8111, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x02, 0x0f);
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bus_isa, 0x0f, apicid_8111, 0x0f);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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@ -188,46 +265,48 @@ void *smp_write_config_table(void *v)
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/* PCI Ints: Type Trigger Polarity Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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/* On board nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, apicid_8111, 0x13);
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/* On board SATA */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x05<<2)|0, apicid_8111, 0x11);
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, apicid_8111, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, apicid_8111, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, apicid_8111, 0x11);
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/* PCI Slot 3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, apicid_8111, 0x10);
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/* PCI Slot 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|1, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|2, apicid_8111, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|3, apicid_8111, 0x11);
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/* PCI Slot 5 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|1, apicid_8111, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|2, apicid_8111, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|3, apicid_8111, 0x10);
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/* PCI Slot 6 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|0, apicid_8111, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|1, apicid_8111, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|2, apicid_8111, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x04<<2)|3, apicid_8111, 0x13);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
|
|
@ -239,9 +318,51 @@ void *smp_write_config_table(void *v)
|
|||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
void reboot_if_hotswap(void)
|
||||
{
|
||||
/* Hack patch work around for hot swap enable 33mhz problem */
|
||||
device_t dev;
|
||||
uint32_t data;
|
||||
unsigned long htic;
|
||||
int reset;
|
||||
int i;
|
||||
|
||||
reset = 0;
|
||||
printk_debug("Looking for bad PCIX MHz input\n");
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||
data = pci_read_config32(dev, 0xa0);
|
||||
if(!(((data>>16)&0x03)==0x03)) {
|
||||
reset=1;
|
||||
printk_debug("Bad PCIX MHz - Reset\n");
|
||||
}
|
||||
printk_debug("Looking for bad Hot Swap Enable\n");
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||
data = pci_read_config32(dev, 0x48);
|
||||
if(data & 0x0c) {
|
||||
reset=1;
|
||||
printk_debug("Bad Hot Swap start - Reset\n");
|
||||
}
|
||||
if(reset) {
|
||||
/* enable cf9 */
|
||||
dev = dev_find_slot(node_link_to_bus(0, 0), PCI_DEVFN(0x04,3));
|
||||
pci_write_config8(dev, 0x41, 0xf1);
|
||||
/* reset */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
|
||||
htic = pci_read_config32(dev, HT_INIT_CONTROL);
|
||||
htic &= ~HTIC_BIOSR_Detect;
|
||||
pci_write_config32(dev, HT_INIT_CONTROL, htic);
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
else {
|
||||
printk_debug("OK 133MHz & Hot Swap is off\n");
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
reboot_if_hotswap();
|
||||
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue