From 24d024ae24ae5f7ebd241c56ea149ade971fc663 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Fri, 12 Feb 2021 16:07:43 -0700
Subject: [PATCH] soc/amd/cezanne: Enable ACPI_SOC_NVS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This fixes the undefined reference for NVB0, NVB1, and NVB2.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib4ba24b66b9ae7899ccd40f91cdd23074f6afc4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/soc/amd/cezanne/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 9dafe2cdb3..98c3484423 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -9,6 +9,7 @@ if SOC_AMD_CEZANNE
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
+	select ACPI_SOC_NVS
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_VERSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32