x86: Unify arch/io.h and arch/romcc_io.h

Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/x86/include/arch/cpu.h

@@ -141,7 +141,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define X86_VENDOR_UNKNOWN 0xff
 
 #if !defined(__ROMCC__)
-#if !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/device.h>
 
 int cpu_phys_address_size(void);
@@ -162,7 +162,6 @@ struct device;
 struct cpu_driver *find_cpu_driver(struct device *cpu);
 #else
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #endif
 
 struct cpu_info {

src/arch/x86/include/arch/io.h

@@ -163,5 +163,348 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
 	*((volatile uint32_t *)(addr)) = value;
 }
 
+#if defined(__PRE_RAM__) || defined(__SMM__)
+static inline int log2(int value)
+{
+        unsigned int r = 0;
+        __asm__ volatile (
+                "bsrl %1, %0\n\t"
+                "jnz 1f\n\t"
+                "movl $-1, %0\n\t"
+                "1:\n\t"
+                : "=r" (r) : "r" (value));
+        return r;
+
+}
+static inline int log2f(int value)
+{
+        unsigned int r = 0;
+        __asm__ volatile (
+                "bsfl %1, %0\n\t"
+                "jnz 1f\n\t"
+                "movl $-1, %0\n\t"
+                "1:\n\t"
+                : "=r" (r) : "r" (value));
+        return r;
+
+}
+
+#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
+        (((SEGBUS) & 0xFFF) << 20) | \
+        (((DEV) & 0x1F) << 15) | \
+        (((FN) & 0x07) << 12) | \
+        ((WHERE) & 0xFFF))
+
+#define PCI_DEV(SEGBUS, DEV, FN) ( \
+        (((SEGBUS) & 0xFFF) << 20) | \
+        (((DEV) & 0x1F) << 15) | \
+        (((FN)  & 0x07) << 12))
+
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+
+
+#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
+
+typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
+
+/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
+ * We don't need to set %fs, and %gs anymore
+ * Before that We need to use %gs, and leave %fs to other RAM access
+ */
+
+static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
+{
+	unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+	addr = (dev>>4) | where;
+#else
+	addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
+#endif
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	return inb(0xCFC + (addr & 3));
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        return read8(addr);
+}
+#endif
+static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	return pci_mmio_read_config8(dev, where);
+#else
+	return pci_io_read_config8(dev, where);
+#endif
+}
+
+static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
+{
+	unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+        addr = (dev>>4) | where;
+#else
+        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	return inw(0xCFC + (addr & 2));
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
+        return read16(addr);
+}
+#endif
+
+static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	return pci_mmio_read_config16(dev, where);
+#else
+        return pci_io_read_config16(dev, where);
+#endif
+}
+
+
+static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
+{
+	unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+        addr = (dev>>4) | where;
+#else
+        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	return inl(0xCFC);
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
+        return read32(addr);
+}
+#endif
+
+static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	return pci_mmio_read_config32(dev, where);
+#else
+        return pci_io_read_config32(dev, where);
+#endif
+}
+
+static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
+{
+	unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+        addr = (dev>>4) | where;
+#else
+        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outb(value, 0xCFC + (addr & 3));
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
+        write8(addr, value);
+}
+#endif
+
+static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	pci_mmio_write_config8(dev, where, value);
+#else
+        pci_io_write_config8(dev, where, value);
+#endif
+}
+
+
+static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
+{
+        unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+        addr = (dev>>4) | where;
+#else
+        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
+        outl(0x80000000 | (addr & ~3), 0xCF8);
+        outw(value, 0xCFC + (addr & 2));
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
+        write16(addr, value);
+}
+#endif
+
+static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	pci_mmio_write_config16(dev, where, value);
+#else
+	pci_io_write_config16(dev, where, value);
+#endif
+}
+
+
+static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
+{
+	unsigned addr;
+#if !CONFIG_PCI_IO_CFG_EXT
+        addr = (dev>>4) | where;
+#else
+        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
+#endif
+	outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(value, 0xCFC);
+}
+
+#if CONFIG_MMCONF_SUPPORT
+static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
+{
+        unsigned addr;
+        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
+        write32(addr, value);
+}
+#endif
+
+static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
+{
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	pci_mmio_write_config32(dev, where, value);
+#else
+        pci_io_write_config32(dev, where, value);
+#endif
+}
+
+static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value)
+{
+	pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
+}
+
+static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value)
+{
+	pci_write_config16(dev, where, pci_read_config16(dev, where) | value);
+}
+
+static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value)
+{
+	pci_write_config32(dev, where, pci_read_config32(dev, where) | value);
+}
+
+#define PCI_DEV_INVALID (0xffffffffU)
+static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
+{
+        for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
+                unsigned int id;
+                id = pci_io_read_config32(dev, 0);
+                if (id == pci_id) {
+                        return dev;
+                }
+        }
+        return PCI_DEV_INVALID;
+}
+
+static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
+{
+	for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
+		unsigned int id;
+		id = pci_read_config32(dev, 0);
+		if (id == pci_id) {
+			return dev;
+		}
+	}
+	return PCI_DEV_INVALID;
+}
+
+static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+{
+	device_t dev, last;
+
+        dev = PCI_DEV(bus, 0, 0);
+        last = PCI_DEV(bus, 31, 7);
+
+        for(; dev <=last; dev += PCI_DEV(0,0,1)) {
+                unsigned int id;
+                id = pci_read_config32(dev, 0);
+                if (id == pci_id) {
+                        return dev;
+                }
+        }
+        return PCI_DEV_INVALID;
+}
+
+/* Generic functions for pnp devices */
+static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value)
+{
+	unsigned port = dev >> 8;
+	outb(reg, port );
+	outb(value, port +1);
+}
+
+static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg)
+{
+	unsigned port = dev >> 8;
+	outb(reg, port);
+	return inb(port +1);
+}
+
+static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev)
+{
+	unsigned device = dev & 0xff;
+	pnp_write_config(dev, 0x07, device);
+}
+
+static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable)
+{
+	pnp_write_config(dev, 0x30, enable?0x1:0x0);
+}
+
+static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev)
+{
+	return !!pnp_read_config(dev, 0x30);
+}
+
+static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase)
+{
+	pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
+	pnp_write_config(dev, index + 1, iobase & 0xff);
+}
+
+static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index)
+{
+	return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1);
+}
+
+static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq)
+{
+	pnp_write_config(dev, index, irq);
+}
+
+static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq)
+{
+	pnp_write_config(dev, index, drq & 0xff);
+}
+
+#endif /* __PRE_RAM__ */
+
 #endif
 

src/arch/x86/include/arch/romcc_io.h

@@ -1,350 +0,0 @@
-#ifndef ARCH_ROMCC_IO_H
-#define ARCH_ROMCC_IO_H 1
-
-#include <stdint.h>
-
-// arch/io.h is pulled in in many places but it could
-// also be pulled in here for all romcc/romstage code.
-// #include <arch/io.h>
-
-static inline int log2(int value)
-{
-        unsigned int r = 0;
-        __asm__ volatile (
-                "bsrl %1, %0\n\t"
-                "jnz 1f\n\t"
-                "movl $-1, %0\n\t"
-                "1:\n\t"
-                : "=r" (r) : "r" (value));
-        return r;
-
-}
-static inline int log2f(int value)
-{
-        unsigned int r = 0;
-        __asm__ volatile (
-                "bsfl %1, %0\n\t"
-                "jnz 1f\n\t"
-                "movl $-1, %0\n\t"
-                "1:\n\t"
-                : "=r" (r) : "r" (value));
-        return r;
-
-}
-
-#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
-        (((SEGBUS) & 0xFFF) << 20) | \
-        (((DEV) & 0x1F) << 15) | \
-        (((FN) & 0x07) << 12) | \
-        ((WHERE) & 0xFFF))
-
-#define PCI_DEV(SEGBUS, DEV, FN) ( \
-        (((SEGBUS) & 0xFFF) << 20) | \
-        (((DEV) & 0x1F) << 15) | \
-        (((FN)  & 0x07) << 12))
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
-	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-
-#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-
-typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
-
-/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
- * We don't need to set %fs, and %gs anymore
- * Before that We need to use %gs, and leave %fs to other RAM access
- */
-
-static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
-{
-	unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-	addr = (dev>>4) | where;
-#else
-	addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
-#endif
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inb(0xCFC + (addr & 3));
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
-        return read8(addr);
-}
-#endif
-static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	return pci_mmio_read_config8(dev, where);
-#else
-	return pci_io_read_config8(dev, where);
-#endif
-}
-
-static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
-{
-	unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-        addr = (dev>>4) | where;
-#else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
-#endif
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inw(0xCFC + (addr & 2));
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
-        return read16(addr);
-}
-#endif
-
-static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	return pci_mmio_read_config16(dev, where);
-#else
-        return pci_io_read_config16(dev, where);
-#endif
-}
-
-
-static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
-{
-	unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-        addr = (dev>>4) | where;
-#else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
-#endif
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	return inl(0xCFC);
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
-        return read32(addr);
-}
-#endif
-
-static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	return pci_mmio_read_config32(dev, where);
-#else
-        return pci_io_read_config32(dev, where);
-#endif
-}
-
-static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
-{
-	unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-        addr = (dev>>4) | where;
-#else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
-#endif
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	outb(value, 0xCFC + (addr & 3));
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where;
-        write8(addr, value);
-}
-#endif
-
-static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	pci_mmio_write_config8(dev, where, value);
-#else
-        pci_io_write_config8(dev, where, value);
-#endif
-}
-
-
-static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
-{
-        unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-        addr = (dev>>4) | where;
-#else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
-#endif
-        outl(0x80000000 | (addr & ~3), 0xCF8);
-        outw(value, 0xCFC + (addr & 2));
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1);
-        write16(addr, value);
-}
-#endif
-
-static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	pci_mmio_write_config16(dev, where, value);
-#else
-	pci_io_write_config16(dev, where, value);
-#endif
-}
-
-
-static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
-{
-	unsigned addr;
-#if !CONFIG_PCI_IO_CFG_EXT
-        addr = (dev>>4) | where;
-#else
-        addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
-#endif
-	outl(0x80000000 | (addr & ~3), 0xCF8);
-	outl(value, 0xCFC);
-}
-
-#if CONFIG_MMCONF_SUPPORT
-static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
-{
-        unsigned addr;
-        addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3);
-        write32(addr, value);
-}
-#endif
-
-static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
-{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
-	pci_mmio_write_config32(dev, where, value);
-#else
-        pci_io_write_config32(dev, where, value);
-#endif
-}
-
-static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value)
-{
-	pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
-}
-
-static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value)
-{
-	pci_write_config16(dev, where, pci_read_config16(dev, where) | value);
-}
-
-static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value)
-{
-	pci_write_config32(dev, where, pci_read_config32(dev, where) | value);
-}
-
-#define PCI_DEV_INVALID (0xffffffffU)
-static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
-{
-        for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
-                unsigned int id;
-                id = pci_io_read_config32(dev, 0);
-                if (id == pci_id) {
-                        return dev;
-                }
-        }
-        return PCI_DEV_INVALID;
-}
-
-static inline device_t pci_locate_device(unsigned pci_id, device_t dev)
-{
-	for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
-		unsigned int id;
-		id = pci_read_config32(dev, 0);
-		if (id == pci_id) {
-			return dev;
-		}
-	}
-	return PCI_DEV_INVALID;
-}
-
-static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
-{
-	device_t dev, last;
-
-        dev = PCI_DEV(bus, 0, 0);
-        last = PCI_DEV(bus, 31, 7);
-
-        for(; dev <=last; dev += PCI_DEV(0,0,1)) {
-                unsigned int id;
-                id = pci_read_config32(dev, 0);
-                if (id == pci_id) {
-                        return dev;
-                }
-        }
-        return PCI_DEV_INVALID;
-}
-
-/* Generic functions for pnp devices */
-static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value)
-{
-	unsigned port = dev >> 8;
-	outb(reg, port );
-	outb(value, port +1);
-}
-
-static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg)
-{
-	unsigned port = dev >> 8;
-	outb(reg, port);
-	return inb(port +1);
-}
-
-static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev)
-{
-	unsigned device = dev & 0xff;
-	pnp_write_config(dev, 0x07, device);
-}
-
-static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable)
-{
-	pnp_write_config(dev, 0x30, enable?0x1:0x0);
-}
-
-static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev)
-{
-	return !!pnp_read_config(dev, 0x30);
-}
-
-static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase)
-{
-	pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
-	pnp_write_config(dev, index + 1, iobase & 0xff);
-}
-
-static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index)
-{
-	return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1);
-}
-
-static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq)
-{
-	pnp_write_config(dev, index, irq);
-}
-
-static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq)
-{
-	pnp_write_config(dev, index, drq & 0xff);
-}
-
-#endif /* ARCH_ROMCC_IO_H */

src/cpu/intel/haswell/bootblock.c

@@ -23,7 +23,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "haswell.h"

src/cpu/intel/haswell/romstage.c

@@ -30,7 +30,6 @@
 #include <timestamp.h>
 #include <arch/io.h>
 #include <arch/stages.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <cbmem.h>

src/cpu/intel/model_206ax/bootblock.c

@@ -23,7 +23,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"

src/cpu/x86/smm/smihandler.c

@@ -20,7 +20,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>

src/cpu/x86/smm/smiutil.c

@@ -20,7 +20,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>

src/cpu/x86/smm/smm_module_handler.c

@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 

src/drivers/oxford/oxpcie/oxpcie_early.c

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/car.h>
 #include <delay.h>
 #include <uart8250.h>

src/ec/acpi/ec.c

@@ -138,6 +138,8 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg)
 	ec_data_reg = data_reg;
 }
 
+#if !defined(__SMM__) && !defined(__PRE_RAM__)
 struct chip_operations ec_acpi_ops = {
 	CHIP_NAME("ACPI Embedded Controller")
 };
+#endif

src/ec/google/chromeec/ec.c

@@ -21,12 +21,9 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <delay.h>
-
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
 #include <device/device.h>
 #include <device/pnp.h>
+#ifndef __PRE_RAM__
 #include <elog.h>
 #include <stdlib.h>
 #include <string.h>

src/ec/quanta/ene_kb3940q/ec.c

@@ -22,10 +22,10 @@
 #ifndef __PRE_RAM__
 
 #include <console/console.h>
+#include <arch/io.h>
 #include <device/device.h>
 #include <device/pnp.h>
 #include <stdlib.h>
-#include <arch/io.h>
 #include <delay.h>
 #include <elog.h>
 #include "ec.h"

src/ec/smsc/mec1308/ec.c

@@ -119,6 +119,7 @@ void ec_set_ports(u16 cmd_reg, u16 data_reg)
 	ec_data_reg = data_reg;
 }
 
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
 static void mec1308_enable(device_t dev)
 {
 	struct ec_smsc_mec1308_config *conf = dev->chip_info;
@@ -133,3 +134,4 @@ struct chip_operations ec_smsc_mec1308_ops = {
 	CHIP_NAME("SMSC MEC1308 EC Mailbox Interface")
 	.enable_dev = mec1308_enable
 };
+#endif

src/include/cpu/cpu.h

@@ -3,7 +3,7 @@
 
 #include <arch/cpu.h>
 
-#if !defined(__ROMCC__)
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
 void cpu_initialize(unsigned int cpu_index);
 struct bus;
 void initialize_cpus(struct bus *cpu_bus);
@@ -20,6 +20,6 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
 extern struct cpu_driver cpu_drivers[];
 /** end of compile time generated pci driver array */
 extern struct cpu_driver ecpu_drivers[];
-#endif /* !__ROMCC__ */
+#endif /* !__PRE_RAM__ && !__SMM__ */
 
 #endif /* CPU_CPU_H */

src/include/device/device.h

@@ -1,6 +1,7 @@
 #ifndef DEVICE_H
 #define DEVICE_H
 
+#ifndef __SMM__
 #include <stdint.h>
 #include <stddef.h>
 #include <device/resource.h>
@@ -222,4 +223,7 @@ ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus,
 ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus,
 							unsigned int addr);
 #endif
+#else /* __SMM__ */
+#include <arch/io.h>
+#endif /* __SMM__ */
 #endif /* DEVICE_H */

src/include/device/pci.h

@@ -20,7 +20,7 @@
 #include <device/pci_def.h>
 #include <device/resource.h>
 #include <device/device.h>
-#ifndef __PRE_RAM__
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
 #include <device/pci_ops.h>
 #include <device/pci_rom.h>
 

src/include/device/pci_ops.h

@@ -1,6 +1,7 @@
 #ifndef PCI_OPS_H
 #define PCI_OPS_H
 
+#ifndef __SMM__
 #include <stdint.h>
 #include <device/device.h>
 #include <arch/pci_ops.h>
@@ -20,5 +21,6 @@ void pci_mmio_write_config8(device_t dev, unsigned int where, u8 val);
 void pci_mmio_write_config16(device_t dev, unsigned int where, u16 val);
 void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val);
 #endif
+#endif
 
 #endif /* PCI_OPS_H */

src/include/device/pnp.h

@@ -5,6 +5,7 @@
 #include <device/device.h>
 #include <device/pnp_def.h>
 
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
 /* Primitive PNP resource manipulation */
 void pnp_write_config(device_t dev, u8 reg, u8 value);
 u8 pnp_read_config(device_t dev, u8 reg);
@@ -50,4 +51,5 @@ struct resource *pnp_get_resource(device_t dev, unsigned index);
 void pnp_enable_devices(struct device *dev, struct device_operations *ops,
 			unsigned int functions, struct pnp_info *info);
 
+#endif
 #endif /* DEVICE_PNP_H */

src/include/lib.h

@@ -24,7 +24,7 @@
 #include <stdint.h>
 #ifndef __ROMCC__ /* romcc doesn't support prototypes. */
 
-#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */
+#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
 /* Defined in src/lib/clog2.c */
 unsigned long log2(unsigned long x);
 #endif

src/lib/ne2k.c

@@ -38,7 +38,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
 #include <ip_checksum.h>
 #include <console/ne2k.h>
 #include <arch/io.h>
-//#include <arch/romcc_io.h>
 
 #define MEM_SIZE MEM_32768
 #define TX_START 64
@@ -343,8 +342,6 @@ void ne2k_transmit(unsigned int eth_nic_base) {
 
 #ifdef __PRE_RAM__
 
-#include <arch/romcc_io.h>
-
 static void ns8390_reset(unsigned int eth_nic_base)
 {
 	int i;

src/mainboard/a-trend/atc-6220/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/a-trend/atc-6240/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "southbridge/intel/i82371eb/i82371eb.h"

src/mainboard/advansus/a785e-i/reset.c

@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <reset.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/advansus/a785e-i/romstage.c

@@ -32,7 +32,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/advantech/pcm-5820/romstage.c

@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/amd/bimini_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/dbm690t/romstage.c

@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/amd/dinar/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/dinar/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>

src/mainboard/amd/inagua/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/inagua/romstage.c

@@ -25,7 +25,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/mahogany/romstage.c

@@ -27,7 +27,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/parmer/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/persimmon/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/persimmon/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/pistachio/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/amd/serengeti_cheetah/ap_romstage.c

@@ -5,7 +5,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include "console/console.c"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -8,7 +8,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/south_station/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/south_station/romstage.c

@@ -25,7 +25,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/thatcher/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/amd/torpedo/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/torpedo/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>

src/mainboard/amd/union_station/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/amd/union_station/romstage.c

@@ -25,7 +25,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/aopen/dxplplusu/romstage.c

@@ -20,7 +20,6 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/arima/hdama/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/artecgroup/dbe61/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asi/mb_5blgp/romstage.c

@@ -21,7 +21,6 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/asi/mb_5blmp/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/asrock/939a785gmh/romstage.c

@@ -28,7 +28,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/asrock/e350m1/reset.c

@@ -17,10 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
 #include <reset.h>
-#include <arch/io.h>		/*inb, outb*/
-#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/asrock/e350m1/romstage.c

@@ -24,7 +24,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/a8n_e/romstage.c

@@ -29,7 +29,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/asus/a8v-e_deluxe/romstage.c

@@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/asus/a8v-e_se/romstage.c

@@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/asus/dsbf/romstage.c

@@ -23,7 +23,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>

src/mainboard/asus/k8v-x/romstage.c

@@ -29,7 +29,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/asus/m2n-e/romstage.c

@@ -30,7 +30,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>

src/mainboard/asus/m2v/romstage.c

@@ -33,7 +33,6 @@ unsigned int get_sbdn(unsigned bus);
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>

src/mainboard/asus/m4a78-em/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/asus/m4a785-m/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/asus/m5a88-v/reset.c

@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <reset.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/asus/m5a88-v/romstage.c

@@ -32,7 +32,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/asus/p2b-d/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asus/p2b-ds/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asus/p2b-f/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asus/p2b-ls/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asus/p2b/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/asus/p3b-f/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/avalue/eax-785e/reset.c

@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <reset.h>
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <arch/io.h>
-#include <arch/romcc_io.h>
+#include <reset.h>
 
 #define HT_INIT_CONTROL		0x6C
 #define HTIC_BIOSR_Detect	(1<<5)

src/mainboard/avalue/eax-785e/romstage.c

@@ -32,7 +32,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/axus/tc320/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/azza/pt-6ibd/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/bcom/winnet100/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/amd/gx1/raminit.c"

src/mainboard/bcom/winnetp680/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "northbridge/via/cn700/raminit.h"

src/mainboard/bifferos/bifferboard/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/biostar/m6tba/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/broadcom/blast/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/compaq/deskpro_en_sff_p600/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <lib.h>

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -3,7 +3,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
 #include "cpu/x86/bist.h"

src/mainboard/eaglelion/5bcm/romstage.c

@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/emulation/qemu-x86/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/getac/p470/romstage.c

@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>

src/mainboard/getac/p470/smihandler.c

@@ -20,7 +20,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/i82801gx.h"

src/mainboard/gigabyte/ga-6bxc/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/gigabyte/ga-6bxe/romstage.c

@@ -22,7 +22,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>

src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c

@@ -28,7 +28,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -31,7 +31,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/gigabyte/m57sli/ap_romstage.c

@@ -26,7 +26,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -29,7 +29,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -27,7 +27,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <cpu/amd/model_10xxx_rev.h>