mainboard/google/reef: Enable cr50 TPM interrupt

Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage.  The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.

BUG=chrome-os-partner:53336

Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/reef/Kconfig

@@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_REEF
 	select I2C_TPM
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_I2C_TPM_CR50
 	select TPM2
 
 if BOARD_GOOGLE_BASEBOARD_REEF
@@ -24,6 +25,9 @@ config DRIVER_TPM_I2C_BUS
 config DRIVER_TPM_I2C_ADDR
 	hex "0x50"
 
+config DRIVER_TPM_I2C_IRQ
+	int "60" # GPE0_DW1_28
+
 config CHROMEOS
 	select LID_SWITCH if BASEBOARD_REEF_LAPTOP
 

src/mainboard/google/reef/variants/baseboard/gpio.c

@@ -353,6 +353,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* I2C2 - TPM  */
 	PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
 	PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
+	PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
 	/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
 	PAD_CFG_GPO(GPIO_122, 0, DEEP),		 /* SIO_SPI_2_RXD */
 };