vendorcode/intel/skykabylake: Update FSP UPD header files
Update FSP UPD header files as per version 1.6.0. Below UPDs are added to FspsUpd.h: * DelayUsbPdoProgramming * MeUnconfigIsValid * CpuS3ResumeDataSize * CpuS3ResumeData CQ-DEPEND=CL:*322871,CL:*323186,CL:*322870 BUG=None BRANCH=None TEST=Build and boot on RVP3 and poppy Change-Id: Id51a474764a28eec463285757d0eb8ec7ca13fd1 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/18289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -773,7 +773,8 @@ typedef struct {
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UINT8 HyperThreading;
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/** Offset 0x02D4 - Enable or Disable CPU Ratio Override
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Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable.
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Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. @note If disabled,
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BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting.
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$EN_DIS
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**/
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UINT8 CpuRatioOverride;
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -363,9 +363,16 @@ typedef struct {
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**/
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UINT8 PchLanEnable;
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/** Offset 0x00FC
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/** Offset 0x00FC - Delay USB PDO Programming
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Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0:
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disable, 1: enable
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace3[24];
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UINT8 DelayUsbPdoProgramming;
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/** Offset 0x00FD
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**/
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UINT8 UnusedUpdSpace3[23];
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/** Offset 0x0114 - Enable PCIE RP CLKREQ Support
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Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for
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@ -739,7 +746,7 @@ typedef struct {
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UINT8 SendVrMbxCmd1;
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/** Offset 0x02E4 - CpuS3ResumeMtrrData
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Pointer CPU S3 Resume MTRR Data
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Pointer to CPU S3 Resume MTRR Data
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**/
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UINT32 CpuS3ResumeMtrrData;
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@ -2041,9 +2048,15 @@ typedef struct {
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**/
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UINT8 MeUnconfigOnRtcClear;
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/** Offset 0x0779
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/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid
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The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear.
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$EN_DIS
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**/
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UINT8 ReservedFspsUpd[7];
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UINT8 MeUnconfigIsValid;
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/** Offset 0x077A
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**/
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UINT8 ReservedFspsUpd[6];
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} FSP_S_CONFIG;
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/** Fsp S Test Configuration
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**/
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UINT8 C1e;
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/** Offset 0x07DA - Enable or Disable Package Cstate Demotion
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Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b>
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/** Offset 0x07DA - Enable or Disable Package C-State Demotion
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Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
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(Auto: Enabled for Skylake; Disabled for Kabylake)
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$EN_DIS
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**/
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UINT8 PkgCStateDemotion;
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/** Offset 0x07DB - Enable or Disable Package Cstate UnDemotion
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Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b>
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/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
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Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
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(Auto: Enabled for Skylake; Disabled for Kabylake)
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$EN_DIS
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**/
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UINT8 PkgCStateUnDemotion;
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@ -2772,11 +2787,21 @@ typedef struct {
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**/
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UINT16 PsysPmax;
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/** Offset 0x087E - ReservedCpuPostMemTest
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/** Offset 0x087E - CpuS3ResumeDataSize
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Size of CPU S3 Resume Data
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**/
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UINT16 CpuS3ResumeDataSize;
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/** Offset 0x0880 - CpuS3ResumeData
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Pointer to CPU S3 Resume Data
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**/
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UINT32 CpuS3ResumeData;
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/** Offset 0x0884 - ReservedCpuPostMemTest
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Reserved for CPU Post-Mem Test
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$EN_DIS
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**/
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UINT8 ReservedCpuPostMemTest[12];
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UINT8 ReservedCpuPostMemTest[6];
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/** Offset 0x088A - SgxSinitDataFromTpm
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SgxSinitDataFromTpm default values
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