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soc/intel/broadwell: Drop `struct romstage_params` 

It is no longer necessary.

Change-Id: Ib37c9de83badc6339dca6916aec8c34a43797652
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2021-01-20 22:53:42 +01:00
parent 65f81a7b90
commit 24e4edb376
2 changed files with 11 additions and 17 deletions
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6
src/soc/intel/broadwell/include/soc/romstage.h
View File

@ -5,12 +5,6 @@
#include <soc/pei_data.h> #include <soc/pei_data.h>
struct chipset_power_state;
struct romstage_params {
struct chipset_power_state *power_state;
struct pei_data pei_data;
};
void mainboard_fill_spd_data(struct pei_data *pei_data); void mainboard_fill_spd_data(struct pei_data *pei_data);
void mainboard_post_raminit(const int s3resume); void mainboard_post_raminit(const int s3resume);

22
src/soc/intel/broadwell/romstage.c
View File

@ -26,7 +26,7 @@ __weak void mainboard_post_raminit(const int s3resume)
/* Entry from cpu/intel/car/romstage.c. */ /* Entry from cpu/intel/car/romstage.c. */
void mainboard_romstage_entry(void) void mainboard_romstage_entry(void)
{ {
struct romstage_params rp = { 0 }; struct pei_data pei_data = { 0 };
post_code(0x30); post_code(0x30);
@ -37,9 +37,9 @@ void mainboard_romstage_entry(void)
pch_early_init(); pch_early_init();
/* Get power state */ /* Get power state */
rp.power_state = fill_power_state(); struct chipset_power_state *const power_state = fill_power_state();
elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); elog_boot_notify(power_state->prev_sleep_state == ACPI_S3);
/* Print useful platform information */ /* Print useful platform information */
report_platform_info(); report_platform_info();
@ -50,28 +50,28 @@ void mainboard_romstage_entry(void)
/* Initialize GPIOs */ /* Initialize GPIOs */
init_gpios(mainboard_gpio_config); init_gpios(mainboard_gpio_config);
mainboard_fill_pei_data(&rp.pei_data); mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&rp.pei_data); mainboard_fill_spd_data(&pei_data);
post_code(0x32); post_code(0x32);
timestamp_add_now(TS_BEFORE_INITRAM); timestamp_add_now(TS_BEFORE_INITRAM);
rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; pei_data.boot_mode = power_state->prev_sleep_state;
/* Print ME state before MRC */ /* Print ME state before MRC */
intel_me_status(); intel_me_status();
/* Save ME HSIO version */ /* Save ME HSIO version */
intel_me_hsio_version(&rp.power_state->hsio_version, intel_me_hsio_version(&power_state->hsio_version,
&rp.power_state->hsio_checksum); &power_state->hsio_checksum);
/* Initialize RAM */ /* Initialize RAM */
raminit(&rp.pei_data); raminit(&pei_data);
timestamp_add_now(TS_AFTER_INITRAM); timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); romstage_handoff_init(power_state->prev_sleep_state == ACPI_S3);
mainboard_post_raminit(rp.power_state->prev_sleep_state == ACPI_S3); mainboard_post_raminit(power_state->prev_sleep_state == ACPI_S3);
} }