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mb/google/zork: update G2 TS RST delay time 

in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even
rst delay time already meets spec definition: 10us (minimum).

Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine
on those specific m/b+BOE(G2 TS) panel.

BUG=b:159510906
BRANCH=master
TEST=emerge-zork coreboot
     boot with G2 TS, make sure G2 TS is functional

Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kevin Chiu 2020-06-29 21:31:33 +08:00 committed by Patrick Georgi
parent 72afe02cfc
commit 24e6221706
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/zork/variants/berknip/overridetree.cb
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@ -93,7 +93,7 @@ chip soc/amd/picasso
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
register "generic.probed" = "1" register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
register "generic.reset_delay_ms" = "1" register "generic.reset_delay_ms" = "50"
register "generic.has_power_resource" = "1" register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01" register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end device i2c 40 on end