mb/google/brya/var/agah: Add Power Limits for RPL SKU
Add power limits for the RPL SKUs of Agah. BUG=b:258432915 TEST=build and boot ADL based Agah. RPL based testing when hardware becomes available. Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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@ -7,3 +7,4 @@ romstage-y += memory.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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ramstage-y += variant.c
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ramstage-y += ramstage.c
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/variants.h>
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#include <device/pci_ids.h>
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const struct cpu_power_limits limits[] = {
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/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
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/* All values are for baseline config as per bug:191906315 comment #10 */
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{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
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{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
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{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
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{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
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{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
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/* Following values are for performance config as per document #686872 */
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{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
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{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
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{ PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
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};
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void variant_devtree_update(void)
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{
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size_t total_entries = ARRAY_SIZE(limits);
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variant_update_power_limits(limits, total_entries);
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}
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