mb/google/brya/var/agah: Add Power Limits for RPL SKU

Add power limits for the RPL SKUs of Agah.

BUG=b:258432915
TEST=build and boot ADL based Agah. RPL based testing
when hardware becomes available.

Change-Id: Ie97a9d14f1ee6f65225b7d26e25ff3d902fddc7f
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69419
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Tarun Tuli 2022-11-09 16:57:32 -05:00 committed by Subrata Banik
parent 35bd7afafe
commit 24fb14a643
2 changed files with 25 additions and 0 deletions

View File

@ -7,3 +7,4 @@ romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += variant.c
ramstage-y += ramstage.c

View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <device/pci_ids.h>
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
/* All values are for baseline config as per bug:191906315 comment #10 */
{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
/* Following values are for performance config as per document #686872 */
{ PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
{ PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
};
void variant_devtree_update(void)
{
size_t total_entries = ARRAY_SIZE(limits);
variant_update_power_limits(limits, total_entries);
}