intelblocks/{pmc,p2sb}: Add missing RPL-S PCH IDs for PMC and P2SB

The PMC and P2SB IDs for Raptor Lake-S PCH were missing. Add them based
on doc 619362 rev 2.2.

Change-Id: I5de00adf2d87cf50571abb02b28e7feebdc3911e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77448
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Michał Żygowski 2023-08-25 12:20:17 +02:00
parent a9232d820e
commit 24fba11244
3 changed files with 4 additions and 0 deletions

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@ -3608,6 +3608,7 @@
#define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe #define PCI_DID_INTEL_MTL_IOE_M_PMC 0x7ebe
#define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece #define PCI_DID_INTEL_MTL_IOE_P_PMC 0x7ece
#define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_P_PMC 0x51a1
#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
/* Intel I2C device Ids */ /* Intel I2C device Ids */
#define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61
@ -4292,6 +4293,7 @@
#define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8 #define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8
#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8 #define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
#define PCI_DID_INTEL_RPP_P_P2SB 0x51a0 #define PCI_DID_INTEL_RPP_P_P2SB 0x51a0
#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
/* Intel SRAM device Ids */ /* Intel SRAM device Ids */
#define PCI_DID_INTEL_APL_SRAM 0x5aec #define PCI_DID_INTEL_APL_SRAM 0x5aec

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@ -156,6 +156,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_S_P2SB, PCI_DID_INTEL_ADP_S_P2SB,
PCI_DID_INTEL_ADP_M_P2SB, PCI_DID_INTEL_ADP_M_P2SB,
PCI_DID_INTEL_SPR_SP_P2SB, PCI_DID_INTEL_SPR_SP_P2SB,
PCI_DID_INTEL_RPP_S_P2SB,
0, 0,
}; };

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@ -131,6 +131,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_P_PMC, PCI_DID_INTEL_ADP_P_PMC,
PCI_DID_INTEL_ADP_S_PMC, PCI_DID_INTEL_ADP_S_PMC,
PCI_DID_INTEL_ADP_M_N_PMC, PCI_DID_INTEL_ADP_M_N_PMC,
PCI_DID_INTEL_RPP_S_PMC,
0 0
}; };