mb/samsung: Clean up LPC and IOAPIC configuration
Don't overwrite the LPC decode config of the generic PCH code, move UART init into bootblock_mainboard_early_init() and don't enable the IOAPIC, which is already done by generic code. Change-Id: I90d090f5bff29174e68981fea3c3f04c666b1d28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -17,6 +17,7 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <string.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/lapic.h>
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@ -33,22 +34,10 @@
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#include <superio/smsc/lpc47n207/lpc47n207.h>
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#endif
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#endif
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void mainboard_pch_lpc_setup(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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/* Set COM1/COM2 decode range */
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if (CONFIG(DRIVERS_UART_8250IO))
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
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try_enabling_LPC47N207_uart();
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#if CONFIG(DRIVERS_UART_8250IO)
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/* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
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KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
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try_enabling_LPC47N207_uart();
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#else
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/* Enable SuperIO + EC + KBC */
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
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KBC_LPC_EN);
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#endif
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}
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}
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void mainboard_late_rcba_config(void)
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void mainboard_late_rcba_config(void)
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@ -88,11 +77,6 @@ void mainboard_late_rcba_config(void)
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DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
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DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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/* Enable IOAPIC (generic) */
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RCBA16(OIC) = 0x0100;
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/* PCH BWG says to read back the IOAPIC enable register */
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(void) RCBA16(OIC);
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}
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}
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static const uint8_t *locate_spd(void)
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static const uint8_t *locate_spd(void)
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@ -46,23 +46,6 @@
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#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
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#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
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void mainboard_pch_lpc_setup(void)
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{
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/* Set COM1/COM2 decode range */
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pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
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#if CONFIG(DRIVERS_UART_8250IO)
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/* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
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CNF2_LPC_EN | COMA_LPC_EN);
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try_enabling_LPC47N207_uart();
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#else
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/* Enable SuperIO + PS/2 Keyboard/Mouse */
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pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
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#endif
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}
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void mainboard_late_rcba_config(void)
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void mainboard_late_rcba_config(void)
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{
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{
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/*
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/*
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@ -97,11 +80,6 @@ void mainboard_late_rcba_config(void)
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DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
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DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
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/* Enable IOAPIC (generic) */
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RCBA16(OIC) = 0x0100;
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/* PCH BWG says to read back the IOAPIC enable register */
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(void) RCBA16(OIC);
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}
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}
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static void setup_sio_gpios(void)
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static void setup_sio_gpios(void)
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@ -242,6 +220,9 @@ int mainboard_should_reset_usb(int s3resume)
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void bootblock_mainboard_early_init(void)
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void bootblock_mainboard_early_init(void)
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{
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{
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if (CONFIG(DRIVERS_UART_8250IO))
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try_enabling_LPC47N207_uart();
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setup_sio_gpios();
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setup_sio_gpios();
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/* Early SuperIO setup */
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/* Early SuperIO setup */
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