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hp/dl145_g1: Adding ACPI support 

Basic ACPI support for this old platform. Created by copying and
tweaking similar motherboard ACPI implementations in coreboot.
Works reasonably well under Linux, providing HPET-timers
and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44).
Not tested under Windows.

Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5185
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Oskar Enoksson 2014-02-08 00:17:21 +01:00 committed by Alexandru Gagniuc
parent cb141bce35
commit 2516f2e467
9 changed files with 1945 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/hp/dl145_g1/Kconfig
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@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select QRANK_DIMM_SUPPORT
select DRIVERS_I2C_I2CMUX
select HAVE_ACPI_TABLES
config MAINBOARD_DIR
string

617
src/mainboard/hp/dl145_g1/acpi/amd8111.asl Normal file
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@ -0,0 +1,617 @@
/*
* Copyright 2005 AMD
* Copyright (C) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
*/
//AMD8111
// APIC version of the interrupt routing table
Name (APIC, Package (0x04) {
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
})
// PIC version of the interrupt routing table
Name (PICM, Package (0x04) {
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
})
Name (DNCG, Ones)
Method (_PRT, 0, NotSerialized) {
If (LEqual (^DNCG, Ones)) {
Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
// Update the Device Number according to SBDN
Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
Store (0x00, ^DNCG)
}
If (LNot (PICF)) {
Return (PICM)
} Else {
Return (APIC)
}
}
// AMD8111 System Management I/O Mapped Registers (PMxx)
OperationRegion (PMIO, SystemIO, PMBS, 0xDF)
Field (PMIO, ByteAcc, NoLock, Preserve) {
Offset (0x1E),
SWSM, 8, // Software SMI Trigger (sets GSTS)
Offset (0x28),
GSTS, 16, // Global STatuS
GNBL, 16, // Global SMI enable
Offset (0x30),
STMC, 5, // Miscellaneous SMI Status
Offset (0x32),
ENMC, 5, // Miscellaneous SMI Enable
Offset (0x44),
STC0, 9, // TCO Status 1
Offset (0x46),
STC1, 4, // TCO Status 2
Offset (0xA8),
STHW, 20 // Device monitor SMI Interrupt Enable
}
Device (HPET) {
Name (HPT, 0x00)
Name (_HID, EisaId ("PNP0103"))
Name (_UID, 0x00)
Method (_STA, 0, NotSerialized) {
Return (0x0F)
}
Method (_CRS, 0, Serialized) {
Name (BUF0, ResourceTemplate () {
Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
})
Return (BUF0)
}
}
#include "amd8111_pic.asl"
#include "amd8111_isa.asl"
Device (TP2P) {
// 8111 P2P and it should 0x00030000 when 8131 present
Method (_ADR, 0, NotSerialized) {
Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
}
Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
// result :
// [0] Bit index into GPEx_EN in the GPE block described by FADT.
// [1] The lowest power state from which the system can be awakened.
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x08, 0x03 })
//} Else {
Return (Package (0x02) { 0x08, 0x01 })
//}
}
Device (ETHR) {
Name (_ADR, 0x00010000)
Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x08, 0x03 })
//} Else {
Return (Package (0x02) { 0x08, 0x01 })
//}
}
}
Device (USB0) {
Name (_ADR, 0x00000000)
Method (_PSW, 1, NotSerialized) { // Power State Wake
And (GNBL, 0x7FFF, GNBL)
}
Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x0F, 0x03 })
//} Else {
Return (Package (0x02) { 0x0F, 0x01 })
//}
}
}
Device (USB1) {
Name (_ADR, 0x00000001)
Method (_PSW, 1, NotSerialized) { // Power State Wake
And (GNBL, 0x7FFF, GNBL)
}
Method (_PRW, 0, NotSerialized) { // Power Resource for Wake
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x0F, 0x03 })
//} Else {
Return (Package (0x02) { 0x0F, 0x01 })
//}
}
}
Name (APIC, Package (0x0C) {
Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
})
Name (PICM, Package (0x0C) {
Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
})
Method (_PRT, 0, NotSerialized) {
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}
Device (IDE0) {
Method (_ADR, 0, NotSerialized) {
Return (DADD(\_SB.PCI0.SBDN, 0x00010001))
}
Name (REGF, 0x01)
Method (_REG, 2, NotSerialized) {
If (LEqual (Arg0, 0x02)) {
Store (Arg1, REGF)
}
}
OperationRegion (BAR0, PCI_Config, 0x00, 0x60)
Field (BAR0, ByteAcc, NoLock, Preserve) {
Offset (0x40), // EIDE Controller Configuration Register
SCEN, 1, // Secondary Channel Enable
PCEN, 1, // Primary Channel Enable
, 10,
SPWB, 1, // Secondary Port posted-write buffer for PIO modes enable
SRPB, 1, // RW (controls nothing)
PPWB, 1, // Primary Port posted-write buffer for PIO modes enable
PRPB, 1, // RW (controls nothing)
PM80, 1, // High-speed 80-pin cable enable Primary Master
PS80, 1, // High-speed 80-pin cable enable Primary Slave
SM80, 1, // High-speed 80-pin cable enable Secondary Master
SS80, 1, // High-speed 80-pin cable enable Secondary Slave
, 4, // RW (controls nothing)
Offset (0x48),
SSRT, 4, //
SSPW, 4, //
SMRT, 4, //
SMPW, 4,
PSRT, 4,
PSPW, 4,
PMRT, 4,
PMPW, 4,
SSAD, 2,
SMAD, 2,
PSAD, 2,
PMAD, 2,
Offset (0x4E),
SXRT, 4,
SXPW, 4,
PXRT, 4,
PXPW, 4,
SSUD, 8,
SMUD, 8,
PSUD, 8,
PMUD, 8,
PPDN, 1,
PPDS, 1,
, 2,
SPDN, 1,
SPDS, 1
}
Name (TIM0, Package (0x06) {
Package (0x05) {
0x78,
0xB4,
0xF0,
0x0186,
0x0258
},
Package (0x07) {
0x78,
0x5A,
0x3C,
0x2D,
0x1E,
0x14,
0x0F
},
Package (0x08) {
0x04,
0x03,
0x02,
0x01,
0x00,
0x00,
0x00,
0x00
},
Package (0x03) {
0x02,
0x01,
0x00
},
Package (0x05) {
0x20,
0x22,
0x42,
0x65,
0xA8
},
Package (0x07) {
0xC2,
0xC1,
0xC0,
0xC4,
0xC5,
0xC6,
0xC7
}
})
Name (TMD0, Buffer (0x14) {})
CreateDWordField (TMD0, 0x00, PIO0)
CreateDWordField (TMD0, 0x04, DMA0)
CreateDWordField (TMD0, 0x08, PIO1)
CreateDWordField (TMD0, 0x0C, DMA1)
CreateDWordField (TMD0, 0x10, CHNF)
Device (CHN0) {
Name (_ADR, 0x00)
Method (_STA, 0, NotSerialized) {
If (PCEN) { Return (0x0F) }
Else { Return (0x09) }
}
Method (_GTM, 0, NotSerialized) {
Return (GTM (PMPW, PMRT, PSPW, PSRT, PMUD, PSUD))
}
Method (_STM, 3, NotSerialized) {
Store (Arg0, TMD0)
Store (STM (), Local0)
And (Local0, 0xFF, PSUD)
ShiftRight (Local0, 0x08, Local0)
And (Local0, 0xFF, PMUD)
ShiftRight (Local0, 0x08, Local0)
And (Local0, 0x0F, PSRT)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, PSPW)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, PMRT)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, PMPW)
Store (GTF (0x00, Arg1), ATA0)
Store (GTF (0x01, Arg2), ATA1)
}
Device (DRV0) {
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized) {
Return (RATA (ATA0))
}
}
Device (DRV1) {
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized) {
Return (RATA (ATA1))
}
}
}
Device (CHN1) {
Name (_ADR, 0x01)
Method (_STA, 0, NotSerialized) {
If (SCEN) { Return (0x0F) }
Else { Return (0x09) }
}
Method (_GTM, 0, NotSerialized) {
Return (GTM (SMPW, SMRT, SSPW, SSRT, SMUD, SSUD))
}
Method (_STM, 3, NotSerialized) {
Store (Arg0, TMD0)
Store (STM (), Local0)
And (Local0, 0xFF, SSUD)
ShiftRight (Local0, 0x08, Local0)
And (Local0, 0xFF, SMUD)
ShiftRight (Local0, 0x08, Local0)
And (Local0, 0x0F, SSRT)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, SSPW)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, SMRT)
ShiftRight (Local0, 0x04, Local0)
And (Local0, 0x0F, SMPW)
Store (GTF (0x00, Arg1), ATA2)
Store (GTF (0x01, Arg2), ATA3)
}
Device (DRV0) {
Name (_ADR, 0x00)
Method (_GTF, 0, NotSerialized) {
Return (RATA (ATA2))
}
}
Device (DRV1) {
Name (_ADR, 0x01)
Method (_GTF, 0, NotSerialized) {
Return (RATA (ATA3))
}
}
}
Method (GTM, 6, Serialized) {
Store (Ones, PIO0)
Store (Ones, PIO1)
Store (Ones, DMA0)
Store (Ones, DMA1)
Store (0x1A, CHNF)
If (REGF) {}
Else { Return (TMD0) }
Add (Arg0, Arg1, Local0)
Add (Local0, 0x02, Local0)
Multiply (Local0, 0x1E, PIO0)
Add (Arg2, Arg3, Local0)
Add (Local0, 0x02, Local0)
Multiply (Local0, 0x1E, PIO1)
If (And (Arg4, 0x40)) {
Or (CHNF, 0x01, CHNF)
And (Arg4, 0x07, Local0)
If (LLess (Local0, 0x04)) {
Add (Local0, 0x02, Local0)
Multiply (Local0, 0x1E, DMA0)
} Else {
If (LEqual (Local0, 0x04)) {
Store (0x2D, DMA0)
} Else {
If (LEqual (Local0, 0x05)) {
Store (0x1E, DMA0)
} Else {
If (LEqual (Local0, 0x06)) {
Store (0x14, DMA0)
} Else {
If (LEqual (Local0, 0x07)) {
Store (0x0F, DMA0)
} Else {
Store (PIO0, DMA0)
}
}
}
}
}
} Else {
Store (PIO0, DMA0)
}
If (And (Arg5, 0x40)) {
Or (CHNF, 0x04, CHNF)
And (Arg5, 0x07, Local0)
If (LLess (Local0, 0x04)) {
Add (Local0, 0x02, Local0)
Multiply (Local0, 0x1E, DMA1)
} Else {
If (LEqual (Local0, 0x04)) {
Store (0x2D, DMA1)
} Else {
If (LEqual (Local0, 0x05)) {
Store (0x1E, DMA1)
} Else {
If (LEqual (Local0, 0x06)) {
Store (0x14, DMA1)
} Else {
If (LEqual (Local0, 0x07)) {
Store (0x0F, DMA0)
} Else {
Store (PIO1, DMA1)
}
}
}
}
}
} Else {
Store (PIO1, DMA1)
}
Return (TMD0)
}
Method (STM, 0, Serialized) {
If (REGF) {}
Else { Return (0xFFFFFFFF) }
If (LEqual (PIO0, 0xFFFFFFFF)) {
Store (0xA8, Local1)
} Else {
And (Match (DerefOf (Index (TIM0, 0x00)),
MGE, PIO0, MTR,
0x00, 0x00),
0x07, Local0)
Store (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
Local1)
}
ShiftLeft (Local1, 0x08, Local1)
If (LEqual (PIO1, 0xFFFFFFFF)) {
Or (Local1, 0xA8, Local1)
} Else {
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIO1, MTR,
0x00, 0x00), 0x07, Local0)
Or (DerefOf (Index (DerefOf (Index (TIM0, 0x04)), Local0)),
Local1, Local1)
}
ShiftLeft (Local1, 0x08, Local1)
If (LEqual (DMA0, 0xFFFFFFFF)) {
Or (Local1, 0x03, Local1)
} Else {
If (And (CHNF, 0x01)) {
And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA0, MTR,
0x00, 0x00), 0x07, Local0)
Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
Local1, Local1)
} Else {
Or (Local1, 0x03, Local1)
}
}
ShiftLeft (Local1, 0x08, Local1)
If (LEqual (DMA1, 0xFFFFFFFF)) {
Or (Local1, 0x03, Local1)
} Else {
If (And (CHNF, 0x04)) {
And (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMA1, MTR,
0x00, 0x00), 0x07, Local0)
Or (DerefOf (Index (DerefOf (Index (TIM0, 0x05)), Local0)),
Local1, Local1)
} Else {
Or (Local1, 0x03, Local1)
}
}
Return (Local1)
}
Name (AT01, Buffer (0x07) {
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF
})
Name (AT02, Buffer (0x07) {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90
})
Name (AT03, Buffer (0x07) {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC6
})
Name (AT04, Buffer (0x07) {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91
})
Name (ATA0, Buffer (0x1D) {})
Name (ATA1, Buffer (0x1D) {})
Name (ATA2, Buffer (0x1D) {})
Name (ATA3, Buffer (0x1D) {})
Name (ATAB, Buffer (0x1D) {})
CreateByteField (ATAB, 0x00, CMDC)
Method (GTFB, 3, Serialized) {
Multiply (CMDC, 0x38, Local0)
Add (Local0, 0x08, Local1)
CreateField (ATAB, Local1, 0x38, CMDX)
Multiply (CMDC, 0x07, Local0)
CreateByteField (ATAB, Add (Local0, 0x02), A001)
CreateByteField (ATAB, Add (Local0, 0x06), A005)
Store (Arg0, CMDX)
Store (Arg1, A001)
Store (Arg2, A005)
Increment (CMDC)
}
Method (GTF, 2, Serialized) {
Store (Arg1, Debug)
Store (0x00, CMDC)
Name (ID49, 0x0C00)
Name (ID59, 0x00)
Name (ID53, 0x04)
Name (ID63, 0x0F00)
Name (ID88, 0x0F00)
Name (IRDY, 0x01)
Name (PIOT, 0x00)
Name (DMAT, 0x00)
If (LEqual (SizeOf (Arg1), 0x0200)) {
CreateWordField (Arg1, 0x62, IW49)
Store (IW49, ID49)
CreateWordField (Arg1, 0x6A, IW53)
Store (IW53, ID53)
CreateWordField (Arg1, 0x7E, IW63)
Store (IW63, ID63)
CreateWordField (Arg1, 0x76, IW59)
Store (IW59, ID59)
CreateWordField (Arg1, 0xB0, IW88)
Store (IW88, ID88)
}
Store (0xA0, Local7)
If (Arg0) {
Store (0xB0, Local7)
And (CHNF, 0x08, IRDY)
If (And (CHNF, 0x10)) {
Store (PIO1, PIOT)
} Else {
Store (PIO0, PIOT)
}
If (And (CHNF, 0x04)) {
If (And (CHNF, 0x10)) {
Store (DMA1, DMAT)
} Else {
Store (DMA0, DMAT)
}
} Else {
Store (PIO1, DMAT)
}
} Else {
And (CHNF, 0x02, IRDY)
Store (PIO0, PIOT)
If (And (CHNF, 0x01)) {
Store (DMA0, DMAT)
}
}
If (LAnd (LAnd (And (ID53, 0x04), And (ID88, 0xFF00)), DMAT)) {
Store (Match (DerefOf (Index (TIM0, 0x01)), MLE, DMAT, MTR,
0x00, 0x00), Local1)
If (LGreater (Local1, 0x06)) {
Store (0x06, Local1)
}
GTFB (AT01, Or (0x40, Local1), Local7)
} Else {
If (LAnd (And (ID63, 0xFF00), PIOT)) {
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
0x00, 0x00), 0x07, Local0)
If (Local0) {
If (And (Local0, 0x04)) {
Store (0x02, Local0)
} Else {
Store (0x01, Local0)
}
}
Or (0x20, DerefOf (Index (DerefOf (Index (TIM0, 0x03)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
}
}
If (IRDY) {
And (Match (DerefOf (Index (TIM0, 0x00)), MGE, PIOT, MTR,
0x00, 0x00), 0x07, Local0)
Or (0x08, DerefOf (Index (DerefOf (Index (TIM0, 0x02)), Local0
)), Local1)
GTFB (AT01, Local1, Local7)
} Else {
If (And (ID49, 0x0400)) {
GTFB (AT01, 0x01, Local7)
}
}
If (LAnd (And (ID59, 0x0100), And (ID59, 0xFF))) {
GTFB (AT03, And (ID59, 0xFF), Local7)
}
Store (ATAB, Debug)
Return (ATAB)
}
Method (RATA, 1, NotSerialized) {
CreateByteField (Arg0, 0x00, CMDN)
Multiply (CMDN, 0x38, Local0)
CreateField (Arg0, 0x08, Local0, RETB)
Store (RETB, Debug)
Return (RETB)
}
}
Device (PMF) {
// acpi smbus it should be 0x00040003 if 8131 present
Method (_ADR, 0, NotSerialized)
{
Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
}
OperationRegion (BAR0, PCI_Config, 0x00, 0xff)
Field (BAR0, ByteAcc, NoLock, Preserve) {
Offset (0x56),
PIRA, 4,
PIRB, 4,
PIRC, 4,
PIRD, 4
}
//OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
//Field (TS3_, DWordAcc, NoLock, Preserve) {
// PTS3, 16
//}
}

155
src/mainboard/hp/dl145_g1/acpi/amd8111_isa.asl Normal file
View File

@ -0,0 +1,155 @@
/*
* Copyright 2005 AMD
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
*/
//AMD8111 isa
Device (ISA) {
// lpc 0x00040000
Method (_ADR, 0, NotSerialized) {
Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
}
/*
OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
Field (PIRY, ByteAcc, NoLock, Preserve) {
Z000, 2, // Parallel Port Range
, 1,
ECP , 1, // ECP Enable
FDC1, 1, // Floppy Drive Controller 1
FDC2, 1, // Floppy Drive Controller 2
Offset (0x01),
Z001, 3, // Serial Port A Range
SAEN, 1, // Serial Post A Enabled
Z002, 3, // Serial Port B Range
SBEN, 1 // Serial Post B Enabled
}
*/
Device (PIC) {
Name (_HID, EisaId ("PNP0000"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x0020, 0x0020, 0x01, 0x02) // Master Interrupt controller
IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02) // Slave Interrupt controller
IRQ (Edge, ActiveHigh, Exclusive) {2}
})
}
Device (DMA1) {
Name (_HID, EisaId ("PNP0200"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x0000, 0x0000, 0x01, 0x10) // Slave DMA controller
IO (Decode16, 0x0080, 0x0080, 0x01, 0x10) // DMA page registers
IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20) // Master DMA controller
DMA (Compatibility, NotBusMaster, Transfer16) {4}
})
}
Device (TMR) {
Name (_HID, EisaId ("PNP0100"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x0040, 0x0040, 0x01, 0x04) // Programmable Interval timer
IRQ (Edge, ActiveHigh, Exclusive) {0}
})
}
Device (RTC) {
Name (_HID, EisaId ("PNP0B00"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x0070, 0x0070, 0x01, 0x04) // Realtime Clock and CMOS ram
IRQ (Edge, ActiveHigh, Exclusive) {8}
})
}
Device (SPKR) {
Name (_HID, EisaId ("PNP0800"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x0061, 0x0061, 0x01, 0x01) // PC speaker
})
}
Device (COPR) { // Co-processor
Name (_HID, EisaId ("PNP0C04"))
Name (_CRS, ResourceTemplate () {
IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10) // Floating point Error control
IRQ (Edge, ActiveHigh, Exclusive) {13}
})
}
Device (SYSR) { // System control registers (?)
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x00)
Name (CRS, ResourceTemplate () {
IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C)
IO (Decode16, 0x0080, 0x0080, 0x01, 0x01)
IO (Decode16, 0x0084, 0x0084, 0x01, 0x03)
IO (Decode16, 0x0088, 0x0088, 0x01, 0x01)
IO (Decode16, 0x008C, 0x008C, 0x01, 0x03)
IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
// IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
// EISA defined level triggered interrupt control registers
IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02)
// IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
// IO (Decode16, 0xDE00, 0xDE00, 0x00, 0x80)
// IO (Decode16, 0xDE80, 0xDE80, 0x00, 0x80)
IO (Decode16,0xDE00,0xDE00,0x00,0x80)
IO (Decode16,0xDE80,0xDE80,0x00,0x80)
// IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
// IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0D) // PMBS block
IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0E) // SMBS block
IO (Decode16, 0x0000, 0x0000, 0x00, 0x00,_Y0F) // GPBS block
})
Method (_CRS, 0, NotSerialized) {
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MIN, GP00)
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._MAX, GP01)
CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0D._LEN, GP0L)
Store (PMBS, GP00)
Store (PMBS, GP01)
Store (PMLN, GP0L)
If (SMBS) {
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MIN, GP10)
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._MAX, GP11)
CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0E._LEN, GP1L)
Store (SMBS, GP10)
Store (SMBS, GP11)
Store (SMBL, GP1L)
}
If (GPBS) {
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MIN, GP20)
CreateWordField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._MAX, GP21)
CreateByteField (CRS, \_SB.PCI0.ISA.SYSR._Y0F._LEN, GP2L)
Store (GPBS, GP20)
Store (GPBS, GP21)
Store (GPLN, GP2L)
}
Return (CRS)
}
}
Device (MEM) {
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x01)
Method (_CRS, 0, Serialized) {
Name (BUF0, ResourceTemplate () {
Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
})
// Read the Video Memory length
CreateDWordField (BUF0, 0x14, CLEN)
CreateDWordField (BUF0, 0x10, CBAS)
ShiftLeft (VGA1, 0x09, Local0)
Store (Local0, CLEN)
Return (BUF0)
}
}
#include "superio/winbond/w83627hf/acpi/superio.asl"
}

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/*
* Copyright 2005 AMD
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
*/
//AMD8111 pic LNKA B C D
Device (LNKA) {
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized) {
If (LEqual (\_SB.PCI0.PMF.PIRA, 0x00) ) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, Serialized) {
Name (BUFA, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized) {
Store (0x00, \_SB.PCI0.PMF.PIRA )
}
Method (_CRS, 0, Serialized) {
Name (BUFA, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local2)
Store (0x00, Local3)
Store (\_SB.PCI0.PMF.PIRA, Local1)
If (LNot (LEqual (Local1, 0x00))) { // Routing enable
If (LGreater (Local1, 0x07)) {
Subtract (Local1, 0x08, Local1)
ShiftLeft (One, Local1, Local3)
} Else {
If (LGreater (Local1, 0x00)) {
ShiftLeft (One, Local1, Local2)
}
}
Store (Local2, IRA1)
Store (Local3, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized) {
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00)) {
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
Store(Local1,\_SB.PCI0.PMF.PIRA)
}
}
Device (LNKB) {
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized) {
If (LEqual (\_SB.PCI0.PMF.PIRB, 0x00) ) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, Serialized) {
Name (BUFB, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized) {
Store (0x00, \_SB.PCI0.PMF.PIRB )
}
Method (_CRS, 0, Serialized) {
Name (BUFB, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRA1)
CreateByteField (BUFB, 0x02, IRA2)
Store (0x00, Local2)
Store (0x00, Local3)
Store (\_SB.PCI0.PMF.PIRB, Local1)
If (LNot (LEqual (Local1, 0x00))) { // Routing enable
If (LGreater (Local1, 0x07)) {
Subtract (Local1, 0x08, Local1)
ShiftLeft (One, Local1, Local3)
} Else {
If (LGreater (Local1, 0x00)) {
ShiftLeft (One, Local1, Local2)
}
}
Store (Local2, IRA1)
Store (Local3, IRA2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized) {
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00)) {
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
Store(Local1,\_SB.PCI0.PMF.PIRB)
}
}
Device (LNKC) {
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x03)
Method (_STA, 0, NotSerialized) {
If (LEqual (\_SB.PCI0.PMF.PIRC, 0x00) ) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, Serialized) {
Name (BUFA, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFA)
}
Method (_DIS, 0, NotSerialized) {
Store (0x00, \_SB.PCI0.PMF.PIRC )
}
Method (_CRS, 0, Serialized) {
Name (BUFA, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFA, 0x01, IRA1)
CreateByteField (BUFA, 0x02, IRA2)
Store (0x00, Local2)
Store (0x00, Local3)
Store (\_SB.PCI0.PMF.PIRC, Local1)
If (LNot (LEqual (Local1, 0x00))) { // Routing enable
If (LGreater (Local1, 0x07)) {
Subtract (Local1, 0x08, Local1)
ShiftLeft (One, Local1, Local3)
} Else {
If (LGreater (Local1, 0x00)) {
ShiftLeft (One, Local1, Local2)
}
}
Store (Local2, IRA1)
Store (Local3, IRA2)
}
Return (BUFA)
}
Method (_SRS, 1, NotSerialized) {
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00)) {
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
Store(Local1,\_SB.PCI0.PMF.PIRC)
}
}
Device (LNKD) {
Name (_HID, EisaId ("PNP0C0F"))
Name (_UID, 0x04)
Method (_STA, 0, NotSerialized) {
If (LEqual (\_SB.PCI0.PMF.PIRD, 0x00) ) { Return (0x09) } //Disabled
Else { Return (0x0B) } //Enabled
}
Method (_PRS, 0, Serialized) {
Name (BUFB, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {3,5,10,11}
})
Return (BUFB)
}
Method (_DIS, 0, NotSerialized) {
Store (0x00, \_SB.PCI0.PMF.PIRD )
}
Method (_CRS, 0, Serialized) {
Name (BUFB, ResourceTemplate () {
IRQ (Level, ActiveLow, Shared) {}
})
CreateByteField (BUFB, 0x01, IRA1)
CreateByteField (BUFB, 0x02, IRA2)
Store (0x00, Local2)
Store (0x00, Local3)
Store (\_SB.PCI0.PMF.PIRD, Local1)
If (LNot (LEqual (Local1, 0x00))) { // Routing enable
If (LGreater (Local1, 0x07)) {
Subtract (Local1, 0x08, Local1)
ShiftLeft (One, Local1, Local3)
} Else {
If (LGreater (Local1, 0x00)) {
ShiftLeft (One, Local1, Local2)
}
}
Store (Local2, IRA1)
Store (Local3, IRA2)
}
Return (BUFB)
}
Method (_SRS, 1, NotSerialized) {
CreateByteField (Arg0, 0x01, IRA1)
CreateByteField (Arg0, 0x02, IRA2)
ShiftLeft (IRA2, 0x08, Local0)
Or (Local0, IRA1, Local0)
Store (0x00, Local1)
ShiftRight (Local0, 0x01, Local0)
While (LGreater (Local0, 0x00)) {
Increment (Local1)
ShiftRight (Local0, 0x01, Local0)
}
Store(Local1,\_SB.PCI0.PMF.PIRD)
}
}

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/*
* Copyright 2005 AMD
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
*/
Device (PG0A) {
/* 8131 pcix bridge 1 */
Method (_ADR, 0, NotSerialized) {
Return (DADD(GHCD(HCIN, 0), 0x00000000))
}
Method (_PRW, 0, NotSerialized) {
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x29, 0x03 })
//} Else {
Return (Package (0x02) { 0x29, 0x01 })
//}
}
Name (APIC, Package (0x0c) {
// Slot 3 - PIRQ BCDA ---- verified
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
// Slot 4 - PIRQ CDAB ---- verified
Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
// Onboard NIC 1 - PIRQ DABC
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
// NIC 2 - PIRQ ABCD -- verified
// Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
// Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
// Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
// Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
// SERIAL ATA - PIRQ BCDA
// Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
// Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
// Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
// Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
})
Name (PICM, Package (0x0c) {
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
// Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
// Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
// Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
// Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
// Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
// Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
// Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
// Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
})
Method (_PRT, 0, NotSerialized) {
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}
Device (PG0B) {
/* 8131 pcix bridge 2 */
Method (_ADR, 0, NotSerialized) {
Return (DADD(GHCD(HCIN, 0), 0x00010000))
}
Method (_PRW, 0, NotSerialized) {
//If (CondRefOf (\_S3, Local0)) {
// Return (Package (0x02) { 0x22, 0x03 })
//} Else {
Return (Package (0x02) { 0x22, 0x01 })
//}
}
Name (APIC, Package (0x04) {
// Slot A - PIRQ CDAB -- verfied
Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },// Slot 2
Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1C },
Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1D },
Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1E }
})
Name (PICM, Package (0x04) {
Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//Slot 2
Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 }
})
Method (_PRT, 0, NotSerialized) {
If (LNot (PICF)) { Return (PICM) }
Else { Return (APIC) }
}
}

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/*
* Copyright (c) 2011, 2014 Oskar Enoksson <enok@lysator.liu.se>
* Subject to the GNU GPL v2, or (at your option) any later version.
*/
#include "amd8111.asl" //real SB at first
#include "amd8131.asl"

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/*
* Island Aruma ACPI support
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2005 Stefan Reinauer
*
* Copyright 2005 AMD
* 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
*
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
* Modified to work with hp/dl145_g1
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdk8_sysconf.h>
#include "northbridge/amd/amdk8/acpi.h"
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
print_debug("\n");
}
#endif
extern unsigned pm_base;
extern const unsigned char AmlCode[];
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern const unsigned char AmlCode_ssdt2[];
extern const unsigned char AmlCode_ssdt3[];
extern const unsigned char AmlCode_ssdt4[];
extern const unsigned char AmlCode_ssdt5[];
#endif
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
unsigned int gsi_base=0x18;
struct mb_sysconf_t *m;
m = sysconf.mb;
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write 8111 IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
IO_APIC_ADDR, 0);
/* Write all 8131 IOAPICs */
{
device_t dev;
struct resource *res;
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_1,
res->base, gsi_base );
gsi_base+=4;
}
}
dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8131_2,
res->base, gsi_base );
gsi_base+=4;
}
}
/*
int i;
int j = 0;
for(i=1; i< sysconf.hc_possible_num; i++) {
unsigned d = 0;
if(!(sysconf.pci1234[i] & 0x1) ) continue;
// 8131 need to use +4
switch (sysconf.hcid[i]) {
case 1:
d = 7;
break;
case 3:
d = 4;
break;
}
switch (sysconf.hcid[i]) {
case 1:
case 3:
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
res->base, gsi_base );
gsi_base+=d;
}
}
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
res->base, gsi_base );
gsi_base+=d;
}
}
break;
}
j++;
}
*/
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
current, 0, 0, 2, 5 );
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high*/
/* create all subtables for processors */
current = acpi_create_madt_lapic_nmis(current, 5, 1);
/* 1: LINT1 connect to NMI */
return current;
}
unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
k8acpi_write_vars();
return (unsigned long) (acpigen_get_current());
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
/* Align ACPI tables to 16byte */
start = ( start + 0x0f ) & -0x10;
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
xsdt = (acpi_xsdt_t *) current;
current += sizeof(acpi_xsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
acpi_write_xsdt(xsdt);
/*
* We explicitly add these tables later on:
*/
printk(BIOS_DEBUG, "ACPI: * HPET\n");
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp,hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk(BIOS_DEBUG, "ACPI: * MADT\n");
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current+=madt->header.length;
acpi_add_table(rsdp,madt);
/* SRAT */
printk(BIOS_DEBUG, "ACPI: * SRAT\n");
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current+=srat->header.length;
acpi_add_table(rsdp,srat);
/* SLIT */
printk(BIOS_DEBUG, "ACPI: * SLIT\n");
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current+=slit->header.length;
acpi_add_table(rsdp,slit);
/* SSDT */
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
ssdt = (acpi_header_t *)current;
acpi_create_ssdt_generator(ssdt, "DYNADATA");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
#if CONFIG_ACPI_SSDTX_NUM >= 1
int i;
void *p;
acpi_header_t *ssdtx;
//same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
if((sysconf.pci1234[i] & 1) != 1 ) continue;
uint8_t c;
if(i<7) {
c = (uint8_t) ('4' + i - 1);
}
else {
c = (uint8_t) ('A' + i - 1 - 6);
}
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
current = ( current + 0x07) & -0x08;
ssdtx = (acpi_header_t *)current;
switch(sysconf.hcid[i]) {
case 1: //8132
p = &AmlCode_ssdt2;
break;
case 2: //8151
p = &AmlCode_ssdt3;
break;
case 3: //8131
p = &AmlCode_ssdt4;
break;
default:
//HTX no io apic
p = &AmlCode_ssdt5;
break;
}
memcpy(ssdtx, p, sizeof(acpi_header_t));
current += ssdtx->length;
memcpy(ssdtx, p, ssdtx->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
acpi_add_table(rsdp,ssdtx);
}
#endif
/* FACS */
printk(BIOS_DEBUG, "ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* DSDT */
printk(BIOS_DEBUG, "ACPI: * DSDT\n");
dsdt = (acpi_header_t *)current;
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FADT */
printk(BIOS_DEBUG, "ACPI: * FADT\n");
acpi_fadt_t *fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt,facs,dsdt);
acpi_add_table(rsdp,fadt);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "xsdt\n");
dump_mem(rsdt, ((void *)xsdt) + sizeof(acpi_xsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* ISA portions taken from QEMU acpi-dsdt.dsl.
*/
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
// Name (SPIO, 0x2E) // SuperIO (w83627hf)
Name (SPI2, 0x4E) // Unknown National Semiconductors (EPM3128A?)
Name (IO1B, 0x0680) // GPIO Base (?)
Name (IO1L, 0x80)
//Name (IO2B, 0x0295) // Hardware monitor
//Name (IO2L, 0x02)
Name (PMBS, 0x2000) // Power Management Base
Name (PMLN, 0xC0) // Power Management Length
Name (GPBS, 0x20C0)
Name (GPLN, 0x20)
Name (SMBS, 0x20E0)
Name (SMBL, 0x20)
#define NO_W83627HF_FDC // don't expose the floppy disk controller
#define NO_W83627HF_FDC_ENUM // don't try to enumerate the connected floppy drives
#define NO_W83627HF_PPORT // don't expose the parallel port
//#define NO_W83627HF_UARTA // don't expose the first serial port
#define NO_W83627HF_UARTB // don't expose the second serial port (already hidden
// if UARTB is configured as IRDA port by firmware)
#define NO_W83627HF_IRDA // don't expose the IRDA port (already hidden if UARTB is
// configured as serial port by firmware)
#define NO_W83627HF_CIR // don't expose the Consumer Infrared functionality
//#define NO_W83627HF_KBC // don't expose the keyboard controller
//#define NO_W83627HF_PS2M // don't expose the PS/2 mouse functionality of the
// keyboard controller
#define NO_W83627HF_GAME // don't expose the game port
#define NO_W83627HF_MIDI // don't expose the MIDI port
// #define NO_W83627HF_HWMON // don't expose the hardware monitor as
// PnP "Motherboard Resource"
// Scope (\_PR) and relevant CPU? objects are auto-generated in SSDT
Scope (\_SB) { // Root of the bus hierarchy
Device (PCI0) { // Top PCI device (AMD K8 Northbridge 1)
Device(MBRS) {
Name (_HID, EisaId ("PNP0C02"))
Name (_UID, 0x01)
External(_CRS) /* Resource Template in SSDT */
}
// The following symbols are assumed to be created by coreboot
External (BUSN)
External (PCIO)
External (MMIO)
External (SBLK)
External (CBST)
External (SBDN)
External (TOM1) // Top Of Memory 1 (low 4GB ?)
External (HCLK) // Hypertransport possible CLocK frequencies
External (HCDN) // Hypertransport Controller Device Numbers
Name (_HID, EisaId ("PNP0A03"))
Name (_ADR, 0x00180000)
//Name (_UID, 0x00)
Name (_UID, 0x01)
Name (HCIN, 0x00) // HC1
Method (_BBN, 0, NotSerialized) {
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
}
Method (_CRS, 0, Serialized) {
Name (BUF0, ResourceTemplate () {
// PCI Configuration address space address/data
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08)
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x8100, // Address Range Minimum
0xFFFF, // Address Range Maximum
0x0000, // Address Translation Offset
0x7F00,,,
, TypeStatic) //8100h-FFFFh
DWordMemory (ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
0x00000000, // Address Space Granularity
0x000C0000, // Address Range Minimum
0x000CFFFF, // Address Range Maximum
0x00000000, // Address Translation Offset
0x00010000,,,
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x0000, // Address Range Minimum
0x03AF, // Address Range Maximum
0x0000, // Address Translation Offset
0x03B0,,,
, TypeStatic) //0-CF7h
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, // Address Space Granularity
0x03E0, // Address Range Minimum
0x0CF7, // Address Range Maximum
0x0000, // Address Translation Offset
0x0918,,,
, TypeStatic) //0-CF7h
})
\_SB.OSTP ()
CreateDWordField (BUF0, 0x3E, VLEN)
CreateDWordField (BUF0, 0x36, VMAX)
CreateDWordField (BUF0, 0x32, VMIN)
ShiftLeft (VGA1, 0x09, Local0)
Add (VMIN, Local0, VMAX)
Decrement (VMAX)
Store (Local0, VLEN)
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
Return (Local3)
}
#include "acpi/pci0_hc.asl"
}
Device (PCI1) {
Name (_HID, "PNP0A03")
Name (_ADR, 0x00190000)
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized) {
Return (\_SB.PCI0.CBST)
}
//Name (HCIN, 0x01) // HC2
//Method (_BBN, 0, NotSerialized) {
// Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
//}
Name (_BBN, 0x00)
}
Device (PWRB) {
Name (_HID, EisaId ("PNP0C0C"))
Name (_UID, 0xAA)
Name (_STA, 0x0B)
}
}
Scope (_GPE) {
Method (_L08, 0, NotSerialized) {
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
Notify (\_SB.PCI0.TP2P.ETHR, 0x02)
Notify (\_SB.PWRB, 0x02)
}
Method (_L0F, 0, NotSerialized) {
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
Notify (\_SB.PCI0.TP2P.USB1, 0x02)
Notify (\_SB.PWRB, 0x02)
}
Method (_L22, 0, NotSerialized) { // GPIO18 (LID) - Pogo 0 Bridge B
Notify (\_SB.PCI0.PG0B, 0x02)
Notify (\_SB.PWRB, 0x02)
}
Method (_L29, 0, NotSerialized) { // GPIO25 (Suspend) - Pogo 0 Bridge A
Notify (\_SB.PCI0.PG0A, 0x02)
Notify (\_SB.PWRB, 0x02)
}
}
OperationRegion (KSB0, SystemIO, 0x72, 0x02) // CMOS ram (?)
Field (KSB0, ByteAcc, NoLock, Preserve) {
KSBI, 8, // Index
KSBD, 8 // Data
}
/*
OperationRegion (IHHM, SystemIO, IO2B, IO2L) // Hardware monitor
Field (IHHM, ByteAcc, NoLock, Preserve) {
HHMI, 8, // Index
HHMD, 8 // Data
}
*/
// Method (_BFS, 1, NotSerialized) {
// Control method executed immediately following a wake event.
// Arg0 => Value of the sleeping state from which woken (1=S1, 2=S2 ...)
// Optional
//}
Method (_PTS, 1, NotSerialized) {
// Control method used to Prepare To Sleep.
// Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
Or (Arg0, 0xF0, Local0)
Store (Local0, DBG8)
}
// Method (_GTS, 1, NotSerialized) {
// Control method executed just prior to setting the sleep enable (SLP_EN) bit.
// Arg0 => Value of the sleeping state (1=S1, 2=S2 ...)
// Optional
//}
// System \_Sx states
// Four bytes must be stored for each supported power state:
// 0:7 Value for PM1a_CNT.SLP_TYP register to enter this system state.
// 8:f Value for PM1b_CNT.SLP_TYP register to enter this system state.
// To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP
// register before the PM1b_CNT.SLP_TYP register.
// 10:1f Reserved
// The states are:
// S0 : Working
// S1 : Sleeping with Processor Context maintained
// S2 : Sleeping with Processor Context not maintained
// S3 : Same as S2, but more power saving (e.g. suspend to RAM)
// S4 : DRAM context not maintained (e.g. suspend to disk)
// S5 : Soft Off
// If only S0 and S5 are declared then no wake-up methods are needed
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
// S1 support should work, but never wakes up, so it's commented out
//Name (\_S1, Package () { 0x01, 0x01, 0x01, 0x01 })
//Name (\_S3, Package () { 0x05, 0x05, 0x05, 0x05 })
Name (\_S5, Package () { 0x07, 0x07, 0x07, 0x07 })
//Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
Method (WAK, 1, NotSerialized) {}
Name (WAKP, Package (0x02) { 0x00, 0x00 })
// Status
// 0: 0 Wake was signaled but failed due to lack of power.
// 1: 1 Wake was signaled but failed due to thermal condition
// 2:31 Reserved
// PSS
// 0:1f If non-zero, the effective S-state the power supply really entered.
Method (_WAK, 1, NotSerialized) {
// System Wake
// Arg0: The value of the sleeping state from which woken (1=S1, ...)
// Result: (2 DWORD package)
ShiftLeft (Arg0, 0x04, DBG8)
WAK (Arg0)
Store (0xFF, KSBI) // Clear 0xFF in CMOS RAM
Store (0x00, KSBD)
If (LEqual (Arg0, 0x01)) { // Wake from S1 state
And (\_SB.PCI0.GSTS, 0x10, Local0)
And (Local0, \_SB.PCI0.GNBL, Local0)
If (Local0) {
Notify (\_SB.PWRB, 0x02)
}
}
Store (\_SB.PCI0.GSTS, \_SB.PCI0.GSTS)
Store (\_SB.PCI0.STMC, \_SB.PCI0.STMC)
Store (\_SB.PCI0.STC0, \_SB.PCI0.STC0)
Store (\_SB.PCI0.STC1, \_SB.PCI0.STC1)
Store (\_SB.PCI0.STHW, \_SB.PCI0.STHW)
If (LEqual (Arg0, 0x03)) { // Wake from S3 state
Notify (\_SB.PCI0.TP2P.USB0, 0x01)
}
Store (0xC0, \_SB.PCI0.SWSM)
If (DerefOf (Index (WAKP, 0x00))) {
Store (0x00, Index (WAKP, 0x01))
} Else {
Store (Arg0, Index (WAKP, 0x01))
}
Return (WAKP)
}
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
Method (_PIC, 1, NotSerialized) { //PIC Flag and Interface Method
// Control method that conveys interrupt model in use to the system
// firmware. OS reports interrupt model in use.
// 0 => PIC Mode
// 1 => APIC Mode
// 2 => SAPIC Mode
// 3.. => Reserved
Store (Arg0, PICF)
}
OperationRegion (DEB8, SystemIO, 0x80, 0x01)
Field (DEB8, ByteAcc, Lock, Preserve) {
DBG8, 8
}
OperationRegion (DEB9, SystemIO, 0x90, 0x01)
Field (DEB9, ByteAcc, Lock, Preserve) {
DBG9, 8
}
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
Field (EXTM, WordAcc, Lock, Preserve) {
AMEM, 32
}
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
Field (VGAM, ByteAcc, Lock, Preserve) {
VGA1, 8 // Video memory length (in 2k units?)
}
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
Field (GRAM, ByteAcc, Lock, Preserve) {
Offset (0x10),
FLG0, 8
}
OperationRegion (Z007, SystemIO, 0x21, 0x01)
Field (Z007, ByteAcc, NoLock, Preserve) {
Z008, 8
}
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
Field (Z009, ByteAcc, NoLock, Preserve) {
Z00A, 8
}
#include "northbridge/amd/amdk8/util.asl"
}

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/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
* (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
* Copyright (C) 2011,2014 Oskar Enoksson <enok@lysator.liu.se>
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
extern unsigned pm_base; /* pm_base should be set in sb acpi */
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
acpi_header_t *header=&(fadt->header);
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt,0,sizeof(acpi_fadt_t));
memcpy(header->signature,"FACP",4);
header->length = 244;
header->revision = 3;
memcpy(header->oem_id,OEM_ID,6);
memcpy(header->oem_table_id,"COREBOOT",8);
memcpy(header->asl_compiler_id,ASLC,4);
header->asl_compiler_revision=0;
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
// 3=Workstation,4=Enterprise Server, 7=Performance Server
fadt->preferred_pm_profile=0x04;
fadt->sci_int=9;
// disable system management mode by setting to 0:
fadt->smi_cmd = 0;//pm_base+0x2f;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = pm_base+0x04;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = 0x0000;
fadt->pm_tmr_blk = pm_base+0x08;
fadt->gpe0_blk = pm_base+0x20;
fadt->gpe1_blk = pm_base+0xb0;
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 0;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 4;
fadt->gpe1_blk_len = 8;
fadt->gpe1_base = 16;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
fadt->flush_size = 0; // ignored if wbindv=1 in flags
fadt->flush_stride = 0; // ignored if wbindv=1 in flags
fadt->duty_offset = 1;
fadt->duty_width = 3; // 0 means duty cycle not supported
// _alrm value 0 means RTC alarm feature not supported
fadt->day_alrm = 0; // 0x7d these have to be
fadt->mon_alrm = 0; // 0x7e added to cmos.layout
fadt->century = 0; // 0x7f to make rtc alrm work
fadt->iapc_boot_arch =
ACPI_FADT_LEGACY_DEVICES |
ACPI_FADT_8042 |
// ACPI_FADT_VGA_NOT_PRESENT |
// ACPI_FADT_MSI_NOT_SUPPORTED|
// ACPI_FADT_NO_PCIE_ASPM_CONTROL|
0;
fadt->res2 = 0;
fadt->flags =
ACPI_FADT_WBINVD |
// ACPI_FADT_WBINVD_FLUSH |
ACPI_FADT_C1_SUPPORTED |
// ACPI_FADT_C2_MP_SUPPORTED |
// ACPI_FADT_POWER_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
// ACPI_FADT_FIXED_RTC |
// ACPI_FADT_S4_RTC_WAKE |
// ACPI_FADT_32BIT_TIMER |
// ACPI_FADT_DOCKING_SUPPORTED|
// ACPI_FADT_RESET_REGISTER |
// ACPI_FADT_SEALED_CASE |
// ACPI_FADT_HEADLESS |
// ACPI_FADT_SLEEP_TYPE |
// ACPI_FADT_PCI_EXPRESS_WAKE |
// ACPI_FADT_PLATFORM_CLOCK |
// ACPI_FADT_S4_RTC_VALID |
// ACPI_FADT_REMOTE_POWER_ON |
// ACPI_FADT_APIC_CLUSTER |
// ACPI_FADT_APIC_PHYSICAL |
0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->res3 = 0;
fadt->res4 = 0;
fadt->res5 = 0;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = pm_base;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = pm_base+0x20;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = pm_base+0xb0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}