northbridge/via/cn700: Add IORESOURCE_BRIDGE resources to AGP bridge
Without them the BS_DEV_RESOURCES stage won't traverse the bridge and the graphics controller would be left without resources assigned. Even worse, the resources would stay based in offset 0 which confuses the MTRR setting code and causes a good chunk of the DRAM to be set to type write combining. With the patch applied, the resources are set: Show resources in subtree (Root Device)...After assigning values. ... PCI: 00:01.0 child on link 0 PCI: 01:00.0 + PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0 + PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1 + PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2 PCI: 01:00.0 - PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 - PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 - PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 + PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14 + PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30 And the caching mode is set properly: MTRR: Physical address space: -0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1 -0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6 -0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0 +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6 +0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 The problem was also spot and discussed here: http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18894 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -152,8 +152,38 @@ static void agp_bridge_init(device_t dev)
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pci_write_config8(dev, 0x45, 0x72);
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}
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static void agp_bridge_read_resources(device_t dev)
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{
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struct resource *resource;
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resource = new_resource(dev, 0);
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
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}
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resource = new_resource(dev, 1);
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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resource->limit = 0xfffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
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resource->flags |= IORESOURCE_BRIDGE;
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}
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resource = new_resource(dev, 2);
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if (resource) {
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resource->base = 0;
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resource->size = 0;
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
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}
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}
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static const struct device_operations agp_bridge_operations = {
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.read_resources = DEVICE_NOOP,
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.read_resources = agp_bridge_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = agp_bridge_init,
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