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src/mb: Remove some unneeded includes 

Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-08-11 13:19:23 +02:00 committed by Patrick Georgi
parent e308cc6186
commit 2527648d8c
60 changed files with 0 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/apple/macbook21/mainboard.c
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@ -15,7 +15,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/io.h> #include <arch/io.h>
#include <delay.h> #include <delay.h>
@ -25,7 +24,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <pc80/mc146818rtc.h>
#include <arch/x86/include/arch/acpigen.h> #include <arch/x86/include/arch/acpigen.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>

1
src/mainboard/apple/macbook21/romstage.c
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@ -26,7 +26,6 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <halt.h> #include <halt.h>

1
src/mainboard/apple/macbook21/smihandler.c
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@ -19,7 +19,6 @@
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <southbridge/intel/i82801gx/nvs.h> #include <southbridge/intel/i82801gx/nvs.h>
#include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/i82801gx/i82801gx.h>
#include <pc80/mc146818rtc.h>
#include <delay.h> #include <delay.h>
#define GPE_EC_SCI 12 #define GPE_EC_SCI 12

1
src/mainboard/asus/p5gc-mx/romstage.c
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@ -28,7 +28,6 @@
#include <timestamp.h> #include <timestamp.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/w83627dhg/w83627dhg.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

1
src/mainboard/emulation/qemu-i440fx/romstage.c
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@ -18,7 +18,6 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

1
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
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@ -27,7 +27,6 @@
#include <timestamp.h> #include <timestamp.h>
#include <superio/ite/it8718f/it8718f.h> #include <superio/ite/it8718f/it8718f.h>
#include <superio/ite/common/ite.h> #include <superio/ite/common/ite.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

1
src/mainboard/google/beltino/mainboard.c
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@ -26,7 +26,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h" #include "onboard.h"

1
src/mainboard/google/butterfly/mainboard.c
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@ -23,7 +23,6 @@
#include <console/console.h> #include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <fmap.h> #include <fmap.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/google/butterfly/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
@ -31,7 +30,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#if IS_ENABLED(CONFIG_CHROMEOS) #if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/link/i915.c
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@ -22,7 +22,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

1
src/mainboard/google/link/mainboard.c
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@ -24,7 +24,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/google/link/romstage.c
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@ -23,7 +23,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
@ -32,7 +31,6 @@
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include "ec/google/chromeec/ec.h" #include "ec/google/chromeec/ec.h"
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#include <cbfs.h> #include <cbfs.h>

1
src/mainboard/google/parrot/mainboard.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/google/parrot/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
@ -31,7 +30,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#include <cbfs.h> #include <cbfs.h>
#include "ec/compal/ene932/ec.h" #include "ec/compal/ene932/ec.h"

1
src/mainboard/google/rambi/mainboard.c
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@ -24,7 +24,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

1
src/mainboard/google/slippy/mainboard.c
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@ -23,7 +23,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

1
src/mainboard/google/stout/mainboard.c
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@ -21,7 +21,6 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/google/stout/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
@ -31,7 +30,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#include <bootmode.h> #include <bootmode.h>
#include <cbfs.h> #include <cbfs.h>

2
src/mainboard/intel/baskingridge/mainboard.c
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@ -20,9 +20,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

3
src/mainboard/intel/bayleybay_fsp/mainboard.c
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@ -17,14 +17,11 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

3
src/mainboard/intel/camelbackmountain_fsp/mainboard.c
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@ -17,14 +17,11 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

3
src/mainboard/intel/cougar_canyon2/mainboard.c
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@ -17,12 +17,9 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/intel/cougar_canyon2/romstage.c
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@ -24,7 +24,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <halt.h> #include <halt.h>
@ -38,7 +37,6 @@
#include <southbridge/intel/fsp_bd82x6x/gpio.h> #include <southbridge/intel/fsp_bd82x6x/gpio.h>
#include <southbridge/intel/fsp_bd82x6x/me.h> #include <southbridge/intel/fsp_bd82x6x/me.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "gpio.h" #include "gpio.h"
#define SIO_PORT 0x164e #define SIO_PORT 0x164e

1
src/mainboard/intel/d510mo/mainboard.c
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@ -16,7 +16,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <device/pci.h> #include <device/pci.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>

3
src/mainboard/intel/emeraldlake2/mainboard.c
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@ -17,12 +17,9 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

3
src/mainboard/intel/emeraldlake2/romstage.c
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@ -22,9 +22,7 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h>
#include <superio/smsc/sio1007/chip.h> #include <superio/smsc/sio1007/chip.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
@ -32,7 +30,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#define SIO_PORT 0x164e #define SIO_PORT 0x164e

2
src/mainboard/intel/stargo2/mainboard.c
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@ -20,8 +20,6 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

3
src/mainboard/intel/stargo2/romstage.c
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@ -24,9 +24,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <halt.h> #include <halt.h>
#include <reset.h> #include <reset.h>
#include <fsp_util.h> #include <fsp_util.h>

2
src/mainboard/intel/wtm2/mainboard.c
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@ -20,9 +20,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/kontron/ktqm77/romstage.c
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@ -22,9 +22,7 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>

2
src/mainboard/lenovo/t400/romstage.c
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@ -21,12 +21,10 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cbmem.h> #include <cbmem.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>

1
src/mainboard/lenovo/t420s/smihandler.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/nvs.h>

3
src/mainboard/lenovo/t520/romstage.c
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@ -24,15 +24,12 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cbfs.h> #include <cbfs.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include <device/device.h> #include <device/device.h>

1
src/mainboard/lenovo/t520/smihandler.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/nvs.h>

1
src/mainboard/lenovo/t530/smihandler.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/nvs.h>

1
src/mainboard/lenovo/t60/mainboard.c
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@ -21,7 +21,6 @@
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <pc80/mc146818rtc.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>

1
src/mainboard/lenovo/t60/romstage.c
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@ -26,7 +26,6 @@
#include <lib.h> #include <lib.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

2
src/mainboard/lenovo/x1_carbon_gen1/romstage.c
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@ -25,7 +25,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
@ -33,7 +32,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cbfs.h> #include <cbfs.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)

2
src/mainboard/lenovo/x200/romstage.c
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@ -21,12 +21,10 @@
#include <arch/io.h> #include <arch/io.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cbmem.h> #include <cbmem.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>

1
src/mainboard/lenovo/x201/mainboard.c
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@ -23,7 +23,6 @@
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <pc80/mc146818rtc.h>
#include "dock.h" #include "dock.h"
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/keyboard.h> #include <pc80/keyboard.h>

1
src/mainboard/lenovo/x201/romstage.c
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@ -25,7 +25,6 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>

1
src/mainboard/lenovo/x201/smihandler.c
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@ -23,7 +23,6 @@
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/intel/model_2065x/model_2065x.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <delay.h> #include <delay.h>
#include "dock.h" #include "dock.h"

1
src/mainboard/lenovo/x220/smihandler.c
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@ -19,7 +19,6 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <delay.h> #include <delay.h>
#include <southbridge/intel/bd82x6x/nvs.h> #include <southbridge/intel/bd82x6x/nvs.h>

3
src/mainboard/lenovo/x230/romstage.c
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@ -24,15 +24,12 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cbfs.h> #include <cbfs.h>
void pch_enable_lpc(void) void pch_enable_lpc(void)

1
src/mainboard/lenovo/x60/mainboard.c
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@ -22,7 +22,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <pc80/mc146818rtc.h>
#include "dock.h" #include "dock.h"
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <drivers/lenovo/lenovo.h> #include <drivers/lenovo/lenovo.h>

1
src/mainboard/lenovo/x60/romstage.c
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@ -26,7 +26,6 @@
#include <lib.h> #include <lib.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

1
src/mainboard/lenovo/z61t/mainboard.c
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@ -21,7 +21,6 @@
#include <ec/lenovo/h8/h8.h> #include <ec/lenovo/h8/h8.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/i945.h>
#include <pc80/mc146818rtc.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>

1
src/mainboard/lenovo/z61t/romstage.c
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@ -26,7 +26,6 @@
#include <lib.h> #include <lib.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>

11
src/mainboard/ocp/monolake/mainboard.c
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@ -14,21 +14,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <types.h>
#include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
/* /*
* mainboard_enable is executed as first thing after enumerate_buses(). * mainboard_enable is executed as first thing after enumerate_buses().

11
src/mainboard/ocp/wedge100s/mainboard.c
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@ -14,21 +14,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <types.h>
#include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
/* /*
* mainboard_enable is executed as first thing after enumerate_buses(). * mainboard_enable is executed as first thing after enumerate_buses().

2
src/mainboard/packardbell/ms2290/mainboard.c
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@ -27,8 +27,6 @@
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <arch/x86/include/arch/acpigen.h> #include <arch/x86/include/arch/acpigen.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

1
src/mainboard/packardbell/ms2290/romstage.c
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@ -25,7 +25,6 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>

2
src/mainboard/packardbell/ms2290/smihandler.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/io.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/ibexpeak/nvs.h>
@ -23,7 +22,6 @@
#include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/nehalem.h>
#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/intel/model_2065x/model_2065x.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <pc80/mc146818rtc.h>
#include <delay.h> #include <delay.h>
static void mainboard_smm_init(void) static void mainboard_smm_init(void)

1
src/mainboard/roda/rk9/romstage.c
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@ -26,7 +26,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h> #include <southbridge/intel/i82801ix/i82801ix.h>

3
src/mainboard/samsung/lumpy/mainboard.c
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@ -19,11 +19,8 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <ec/smsc/mec1308/ec.h> #include <ec/smsc/mec1308/ec.h>

2
src/mainboard/samsung/lumpy/romstage.c
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@ -22,7 +22,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <cbfs.h> #include <cbfs.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
@ -33,7 +32,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#include "option_table.h" #include "option_table.h"
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)

10
src/mainboard/samsung/stumpy/mainboard.c
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@ -14,19 +14,9 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <types.h>
#include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <drivers/intel/gma/int15.h> #include <drivers/intel/gma/int15.h>
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/samsung/stumpy/romstage.c
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@ -34,7 +34,6 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h> #include <halt.h>
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) #if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h> #include <superio/smsc/lpc47n207/lpc47n207.h>

1
src/mainboard/siemens/mc_bdx1/mainboard.c
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@ -26,7 +26,6 @@
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>

2
src/mainboard/siemens/mc_tcu3/mainboard.c
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@ -17,14 +17,12 @@
#include <types.h> #include <types.h>
#include <string.h> #include <string.h>
#include <device/device.h> #include <device/device.h>
#include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
#if IS_ENABLED(CONFIG_VGA_ROM_RUN) #if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h> #include <x86emu/x86emu.h>
#endif #endif
#include <pc80/mc146818rtc.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>