src/cpu/power9: add file structure for power9, implement SCOM access
Change-Id: Ib555ce51294c94b22d9a7c0db84d38d7928f7015 Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Igor Bagnucki
Felix Held
parent
3c00c7ec6b
commit
252fc29d1a
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@ -5,4 +5,16 @@
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#define __BIG_ENDIAN 4321
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#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
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#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
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#ifndef __ASSEMBLER__
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#include <types.h>
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#define PPC_SHIFT(val, lsb) (((uint64_t)(val)) << (63 - (lsb)))
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#else
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#define PPC_SHIFT(val, lsb) ((val) << (63 - (lsb)))
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#endif
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#endif /* _BYTEORDER_H */
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@ -9,6 +9,7 @@
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#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
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#define LPCHC_IO_SPACE 0xD0010000
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#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
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#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000
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/* Enforce In-order Execution of I/O */
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static inline void eieio(void)
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@ -7,6 +7,7 @@ subdirs-y += intel
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subdirs-y += ti
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subdirs-$(CONFIG_ARCH_X86) += x86
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subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86
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subdirs-$(CONFIG_CPU_POWER9) += power9
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$(eval $(call create_class_compiler,cpu_microcode,x86_32))
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################################################################################
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@ -0,0 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config CPU_POWER9
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bool
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select ARCH_BOOTBLOCK_PPC64
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select ARCH_VERSTAGE_PPC64
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select ARCH_ROMSTAGE_PPC64
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select ARCH_RAMSTAGE_PPC64
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-y += power9.c
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bootblock-y += scom.c
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romstage-y += scom.c
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/cpu.h>
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#include <device/device.h>
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static void power9_cpu_init(struct device *dev)
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{
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}
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static struct device_operations cpu_dev_ops = {
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.init = power9_cpu_init,
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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};
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struct chip_operations cpu_power8_qemu_ops = {
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CHIP_NAME("POWER9 CPU")
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};
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@ -0,0 +1,135 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/power/scom.h>
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#include <cpu/power/spr.h> // HMER
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#include <console/console.h>
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#define XSCOM_DATA_IND_READ PPC_BIT(0)
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#define XSCOM_DATA_IND_COMPLETE PPC_BIT(32)
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#define XSCOM_DATA_IND_ERR PPC_BITMASK(33, 35)
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#define XSCOM_DATA_IND_DATA PPC_BITMASK(48, 63)
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#define XSCOM_DATA_IND_FORM1_DATA PPC_BITMASK(12, 63)
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#define XSCOM_IND_MAX_RETRIES 10
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#define XSCOM_RCVED_STAT_REG 0x00090018
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#define XSCOM_LOG_REG 0x00090012
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#define XSCOM_ERR_REG 0x00090013
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uint64_t read_scom_direct(uint64_t reg_address)
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{
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uint64_t val;
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uint64_t hmer = 0;
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do {
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/*
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* Clearing HMER on every SCOM access seems to slow down CCS up
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* to a point where it starts hitting timeout on "less ideal"
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* DIMMs for write centering. Clear it only if this do...while
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* executes more than once.
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*/
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if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED)
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clear_hmer();
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eieio();
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asm volatile(
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"ldcix %0, %1, %2" :
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"=r"(val) :
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"b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR),
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"r"(reg_address << 3));
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eieio();
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hmer = read_hmer();
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} while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED);
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if (hmer & SPR_HMER_XSCOM_STATUS) {
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reset_scom_engine();
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/*
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* All F's are returned in case of error, but code polls for a set bit
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* after changes that can make such error appear (e.g. clock settings).
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* Return 0 so caller won't have to test for all F's in that case.
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*/
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return 0;
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}
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return val;
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}
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void write_scom_direct(uint64_t reg_address, uint64_t data)
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{
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uint64_t hmer = 0;
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do {
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/* See comment in read_scom_direct() */
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if ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED)
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clear_hmer();
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eieio();
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asm volatile(
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"stdcix %0, %1, %2"::
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"r"(data),
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"b"(MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR),
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"r"(reg_address << 3));
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eieio();
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hmer = read_hmer();
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} while ((hmer & SPR_HMER_XSCOM_STATUS) == SPR_HMER_XSCOM_OCCUPIED);
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if (hmer & SPR_HMER_XSCOM_STATUS)
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reset_scom_engine();
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}
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void write_scom_indirect(uint64_t reg_address, uint64_t value)
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{
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uint64_t addr;
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uint64_t data;
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addr = reg_address & 0x7FFFFFFF;
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data = reg_address & XSCOM_ADDR_IND_ADDR;
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data |= value & XSCOM_ADDR_IND_DATA;
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write_scom_direct(addr, data);
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for (int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) {
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data = read_scom_direct(addr);
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if ((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) {
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return;
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} else if (data & XSCOM_DATA_IND_COMPLETE) {
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printk(BIOS_EMERG, "SCOM WR error %16.16llx = %16.16llx : %16.16llx\n",
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reg_address, value, data);
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}
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// TODO: delay?
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}
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}
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uint64_t read_scom_indirect(uint64_t reg_address)
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{
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uint64_t addr;
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uint64_t data;
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addr = reg_address & 0x7FFFFFFF;
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data = XSCOM_DATA_IND_READ | (reg_address & XSCOM_ADDR_IND_ADDR);
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write_scom_direct(addr, data);
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for (int retries = 0; retries < XSCOM_IND_MAX_RETRIES; ++retries) {
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data = read_scom_direct(addr);
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if ((data & XSCOM_DATA_IND_COMPLETE) && ((data & XSCOM_DATA_IND_ERR) == 0)) {
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break;
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} else if (data & XSCOM_DATA_IND_COMPLETE) {
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printk(BIOS_EMERG, "SCOM RD error %16.16llx : %16.16llx\n",
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reg_address, data);
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}
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// TODO: delay?
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}
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return data & XSCOM_DATA_IND_DATA;
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}
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/* This function should be rarely called, don't make it inlined */
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void reset_scom_engine(void)
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{
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/*
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* With cross-CPU SCOM accesses, first register should be cleared on the
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* executing CPU, the other two on target CPU. In that case it may be
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* necessary to do the remote writes in assembly directly to skip checking
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* HMER and possibly end in a loop.
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*/
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write_scom_direct(XSCOM_RCVED_STAT_REG, 0);
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write_scom_direct(XSCOM_LOG_REG, 0);
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write_scom_direct(XSCOM_ERR_REG, 0);
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clear_hmer();
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eieio();
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}
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@ -0,0 +1,161 @@
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#ifndef CPU_PPC64_SCOM_H
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#define CPU_PPC64_SCOM_H
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#include <arch/byteorder.h> // PPC_BIT(), PPC_BITMASK()
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// 32b SCOM address:
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//
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// 8 7 6 5 4 3 2 1
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//
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// | | | | | 1 1| |1 1 1 1| |1 1 1 1| |2 2 2 2| |2 2 2 2| |2 2 3 3|
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// |0 1 2 3| |4 5 6 7| |8 9 0 1| |2 3 4 5| |6 7 8 9| |0 1 2 3| |4 5 6 7| |8 9 0 1|
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// {A}{ B } { C } { D }{ E }{ F }
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//
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// A - Is multiCast if bit 1 = 0x1
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// B - Contains Chiplet ID (6 bits) [2:7]
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// C - Contains Port Number (4 bits) [12:15]
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// D - Ring (4 bits) [18:21]
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// E - Sat ID (4 bits) [22:25]
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// F - Sat Offset (6 bits) [26:31]
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//
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// For 64b SCOM address all of the fields are shifted 32b to the right:
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// A - Is multiCast if bit 33 = 0x1
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// B - Contains Chiplet ID (6 bits) [34:39]
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// C - Contains Port Number (4 bits) [44:47]
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// D - Ring (4 bits) [50:53]
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// E - Sat ID (4 bits) [54:57]
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// F - Sat Offset (6 bits) [58:63]
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// Higher bits specify indirect address
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#define XSCOM_ADDR_IND_FLAG PPC_BIT(0)
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#define XSCOM_ADDR_IND_ADDR PPC_BITMASK(11, 31)
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#define XSCOM_ADDR_IND_DATA PPC_BITMASK(48, 63)
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#ifndef __ASSEMBLER__
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#include <types.h>
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#include <arch/io.h>
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#include <cpu/power/spr.h>
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// TODO: these are probably specific to POWER9
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typedef enum {
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PIB_CHIPLET_ID = 0x00, ///< PIB chiplet
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PERV_CHIPLET_ID = 0x01, ///< TP chiplet
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N0_CHIPLET_ID = 0x02, ///< Nest0 (North) chiplet
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N1_CHIPLET_ID = 0x03, ///< Nest1 (East) chiplet
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N2_CHIPLET_ID = 0x04, ///< Nest2 (South) chiplet
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N3_CHIPLET_ID = 0x05, ///< Nest3 (West) chiplet
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XB_CHIPLET_ID = 0x06, ///< XBus chiplet
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MC01_CHIPLET_ID = 0x07, ///< MC01 (West) chiplet
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MC23_CHIPLET_ID = 0x08, ///< MC23 (East) chiplet
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OB0_CHIPLET_ID = 0x09, ///< OBus0 chiplet
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OB1_CHIPLET_ID = 0x0A, ///< OBus1 chiplet (Cumulus only)
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OB2_CHIPLET_ID = 0x0B, ///< OBus2 chiplet (Cumulus only)
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OB3_CHIPLET_ID = 0x0C, ///< OBus3 chiplet
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PCI0_CHIPLET_ID = 0x0D, ///< PCIe0 chiplet
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PCI1_CHIPLET_ID = 0x0E, ///< PCIe1 chiplet
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PCI2_CHIPLET_ID = 0x0F, ///< PCIe2 chiplet
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EP00_CHIPLET_ID = 0x10, ///< Quad0 chiplet (EX0/1)
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EP01_CHIPLET_ID = 0x11, ///< Quad1 chiplet (EX2/3)
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EP02_CHIPLET_ID = 0x12, ///< Quad2 chiplet (EX4/5)
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EP03_CHIPLET_ID = 0x13, ///< Quad3 chiplet (EX6/7)
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EP04_CHIPLET_ID = 0x14, ///< Quad4 chiplet (EX8/9)
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EP05_CHIPLET_ID = 0x15, ///< Quad5 chiplet (EX10/11)
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EC00_CHIPLET_ID = 0x20, ///< Core0 chiplet (Quad0, EX0, C0)
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EC01_CHIPLET_ID = 0x21, ///< Core1 chiplet (Quad0, EX0, C1)
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EC02_CHIPLET_ID = 0x22, ///< Core2 chiplet (Quad0, EX1, C0)
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EC03_CHIPLET_ID = 0x23, ///< Core3 chiplet (Quad0, EX1, C1)
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EC04_CHIPLET_ID = 0x24, ///< Core4 chiplet (Quad1, EX2, C0)
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EC05_CHIPLET_ID = 0x25, ///< Core5 chiplet (Quad1, EX2, C1)
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EC06_CHIPLET_ID = 0x26, ///< Core6 chiplet (Quad1, EX3, C0)
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EC07_CHIPLET_ID = 0x27, ///< Core7 chiplet (Quad1, EX3, C1)
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EC08_CHIPLET_ID = 0x28, ///< Core8 chiplet (Quad2, EX4, C0)
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EC09_CHIPLET_ID = 0x29, ///< Core9 chiplet (Quad2, EX4, C1)
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EC10_CHIPLET_ID = 0x2A, ///< Core10 chiplet (Quad2, EX5, C0)
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EC11_CHIPLET_ID = 0x2B, ///< Core11 chiplet (Quad2, EX5, C1)
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EC12_CHIPLET_ID = 0x2C, ///< Core12 chiplet (Quad3, EX6, C0)
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EC13_CHIPLET_ID = 0x2D, ///< Core13 chiplet (Quad3, EX6, C1)
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EC14_CHIPLET_ID = 0x2E, ///< Core14 chiplet (Quad3, EX7, C0)
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EC15_CHIPLET_ID = 0x2F, ///< Core15 chiplet (Quad3, EX7, C1)
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EC16_CHIPLET_ID = 0x30, ///< Core16 chiplet (Quad4, EX8, C0)
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EC17_CHIPLET_ID = 0x31, ///< Core17 chiplet (Quad4, EX8, C1)
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EC18_CHIPLET_ID = 0x32, ///< Core18 chiplet (Quad4, EX9, C0)
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EC19_CHIPLET_ID = 0x33, ///< Core19 chiplet (Quad4, EX9, C1)
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EC20_CHIPLET_ID = 0x34, ///< Core20 chiplet (Quad5, EX10, C0)
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EC21_CHIPLET_ID = 0x35, ///< Core21 chiplet (Quad5, EX10, C1)
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EC22_CHIPLET_ID = 0x36, ///< Core22 chiplet (Quad5, EX11, C0)
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EC23_CHIPLET_ID = 0x37 ///< Core23 chiplet (Quad5, EX11, C1)
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} chiplet_id_t;
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void reset_scom_engine(void);
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uint64_t read_scom_direct(uint64_t reg_address);
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void write_scom_direct(uint64_t reg_address, uint64_t data);
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uint64_t read_scom_indirect(uint64_t reg_address);
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void write_scom_indirect(uint64_t reg_address, uint64_t data);
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static inline void write_scom(uint64_t addr, uint64_t data)
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{
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if (addr & XSCOM_ADDR_IND_FLAG)
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write_scom_indirect(addr, data);
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else
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write_scom_direct(addr, data);
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}
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static inline uint64_t read_scom(uint64_t addr)
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{
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if (addr & XSCOM_ADDR_IND_FLAG)
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return read_scom_indirect(addr);
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else
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return read_scom_direct(addr);
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}
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static inline void scom_and_or(uint64_t addr, uint64_t and, uint64_t or)
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{
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uint64_t data = read_scom(addr);
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write_scom(addr, (data & and) | or);
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}
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static inline void scom_and(uint64_t addr, uint64_t and)
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{
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scom_and_or(addr, and, 0);
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}
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static inline void scom_or(uint64_t addr, uint64_t or)
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{
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scom_and_or(addr, ~0, or);
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}
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static inline void write_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t data)
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{
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addr &= ~PPC_BITMASK(34, 39);
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addr |= ((chiplet & 0x3F) << 24);
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write_scom(addr, data);
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}
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static inline uint64_t read_scom_for_chiplet(chiplet_id_t chiplet, uint64_t addr)
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{
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addr &= ~PPC_BITMASK(34, 39);
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addr |= ((chiplet & 0x3F) << 24);
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return read_scom(addr);
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}
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static inline void scom_and_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr,
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uint64_t and, uint64_t or)
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{
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uint64_t data = read_scom_for_chiplet(chiplet, addr);
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write_scom_for_chiplet(chiplet, addr, (data & and) | or);
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}
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static inline void scom_and_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t and)
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{
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scom_and_or_for_chiplet(chiplet, addr, and, 0);
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}
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static inline void scom_or_for_chiplet(chiplet_id_t chiplet, uint64_t addr, uint64_t or)
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{
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scom_and_or_for_chiplet(chiplet, addr, ~0, or);
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}
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#endif /* __ASSEMBLER__ */
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#endif /* CPU_PPC64_SCOM_H */
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@ -0,0 +1,70 @@
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#ifndef CPU_PPC64_SPR_H
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#define CPU_PPC64_SPR_H
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#include <arch/byteorder.h> // PPC_BIT()
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#define SPR_TB 0x10C
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#define SPR_PVR 0x11F
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#define SPR_PVR_REV_MASK (PPC_BITMASK(52, 55) | PPC_BITMASK(60, 63))
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#define SPR_PVR_REV(maj, min) (PPC_SHIFT((maj), 55) | PPC_SHIFT((min), 63))
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||||
|
||||
#define SPR_HRMOR 0x139
|
||||
|
||||
#define SPR_HMER 0x150
|
||||
/* Bits in HMER/HMEER */
|
||||
#define SPR_HMER_MALFUNCTION_ALERT PPC_BIT(0)
|
||||
#define SPR_HMER_PROC_RECV_DONE PPC_BIT(2)
|
||||
#define SPR_HMER_PROC_RECV_ERROR_MASKED PPC_BIT(3)
|
||||
#define SPR_HMER_TFAC_ERROR PPC_BIT(4)
|
||||
#define SPR_HMER_TFMR_PARITY_ERROR PPC_BIT(5)
|
||||
#define SPR_HMER_XSCOM_FAIL PPC_BIT(8)
|
||||
#define SPR_HMER_XSCOM_DONE PPC_BIT(9)
|
||||
#define SPR_HMER_PROC_RECV_AGAIN PPC_BIT(11)
|
||||
#define SPR_HMER_WARN_RISE PPC_BIT(14)
|
||||
#define SPR_HMER_WARN_FALL PPC_BIT(15)
|
||||
#define SPR_HMER_SCOM_FIR_HMI PPC_BIT(16)
|
||||
#define SPR_HMER_TRIG_FIR_HMI PPC_BIT(17)
|
||||
#define SPR_HMER_HYP_RESOURCE_ERR PPC_BIT(20)
|
||||
#define SPR_HMER_XSCOM_STATUS PPC_BITMASK(21, 23)
|
||||
#define SPR_HMER_XSCOM_OCCUPIED PPC_BIT(23)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <types.h>
|
||||
|
||||
static inline uint64_t read_spr(int spr)
|
||||
{
|
||||
uint64_t val;
|
||||
asm volatile("mfspr %0,%1" : "=r"(val) : "i"(spr) : "memory");
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void write_spr(int spr, uint64_t val)
|
||||
{
|
||||
asm volatile("mtspr %0, %1" :: "i"(spr), "r"(val) : "memory");
|
||||
}
|
||||
|
||||
static inline uint64_t read_hmer(void)
|
||||
{
|
||||
return read_spr(SPR_HMER);
|
||||
}
|
||||
|
||||
static inline void clear_hmer(void)
|
||||
{
|
||||
write_spr(SPR_HMER, 0);
|
||||
}
|
||||
|
||||
static inline uint64_t read_msr(void)
|
||||
{
|
||||
uint64_t val;
|
||||
asm volatile("mfmsr %0" : "=r"(val) :: "memory");
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline uint64_t pvr_revision(void)
|
||||
{
|
||||
return read_spr(SPR_PVR) & SPR_PVR_REV_MASK;
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* CPU_PPC64_SPR_H */
|
||||
Loading…
Reference in New Issue