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soc/intel/common/gpio: Add PCH `Pad Configuration Lock` options 

This patch provides the possible options for PCH to allow `Pad
Configuration Lock`.

`SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake
Point (TGP) and Alder Lake Point (ADP) PCH.

BUG=b:211573253, b:211950520
TEST=None

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Subrata Banik 2022-01-10 09:15:56 +00:00 committed by Felix Held
parent 6a4f5739c8
commit 25387927c0
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/common/block/gpio/Kconfig
View File

@ -36,4 +36,19 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
bool
default n
config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
bool
default n
help
From TGL PCH onwards,`Pad Configuration Lock` can only be set or cleared
using non-posted sideband write.
config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR
bool
default n
depends on !SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI
help
SoC user to select this config if `Pad Configuration Lock` can only be set or
cleared using private configuration register (PCR) write.
endif