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mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY

Browse source 
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).

Thus, drop the setting from all devicetrees.

Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Michael Niewöhner 2020-09-05 13:47:11 +02:00 committed by Michael Niewöhner
parent 056d552357
commit 2539a67273
43 changed files with 0 additions and 211 deletions
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8
src/mainboard/facebook/monolith/devicetree.cb
View file

@ -192,21 +192,13 @@ chip soc/intel/skylake
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB3_TYPE-A Port 2
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 1
register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # M2 Port
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # Audio board
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled
# USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 2
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3_TYPE-A Port 2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C Port 1
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SsicPortEnable" = "0"

4
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
View file

@ -32,16 +32,12 @@ chip soc/intel/jasperlake
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Not Used
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not Used
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Not Used
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Not Used
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

3
src/mainboard/google/dedede/variants/madoo/overridetree.cb
View file

@ -1,10 +1,7 @@
chip soc/intel/jasperlake
# USB Port Configuration
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Not Used
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Not Used
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not Used
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

3
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
View file

@ -38,16 +38,13 @@ chip soc/intel/tigerlake
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 2
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Ext USB Port 1 (Right)
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Ext USB Port 2 (Left)
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # M.2 3042 (WWAN)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB Port 2
register "usb3_ports[2]" = "USB3_PORT_EMPTY"
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# PCIe root port 7 (Card Reader), clock 4

4
src/mainboard/google/drallion/variants/drallion/devicetree.cb
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@ -152,9 +152,6 @@ chip soc/intel/cannonlake
register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port
@ -162,7 +159,6 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

3
src/mainboard/google/eve/devicetree.cb
View file

@ -153,12 +153,9 @@ chip soc/intel/skylake
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View file

@ -248,7 +248,6 @@ chip soc/intel/skylake
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A 2.0 / Debug
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear

3
src/mainboard/google/fizz/variants/endeavour/overridetree.cb
View file

@ -49,15 +49,12 @@ chip soc/intel/skylake
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-A Rear
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # HDMI Audio
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # None
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # H1 (disconnected)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Rear
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # None
register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # TPU
register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM

4
src/mainboard/google/glados/variants/caroline/overridetree.cb
View file

@ -13,14 +13,10 @@ chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main)
register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Empty
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (main)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (sub)
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# PL2 override 15W
register "power_limits_config" = "{

4
src/mainboard/google/glados/variants/cave/overridetree.cb
View file

@ -6,14 +6,10 @@ chip soc/intel/skylake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port (board)
register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (flex)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Type-A Port 1
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A Port 2
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (board)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port (flex)
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2
# PL2 override 15W
register "power_limits_config" = "{

8
src/mainboard/google/hatch/variants/akemi/overridetree.cb
View file

@ -22,20 +22,12 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Unused
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # WWAN
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Unused
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

4
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View file

@ -157,11 +157,8 @@ chip soc/intel/cannonlake
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
@ -169,7 +166,6 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"

3
src/mainboard/google/hatch/variants/duffy/overridetree.cb
View file

@ -66,9 +66,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,

2
src/mainboard/google/hatch/variants/faffy/overridetree.cb
View file

@ -74,8 +74,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # PL2303
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,

3
src/mainboard/google/hatch/variants/kaisa/overridetree.cb
View file

@ -66,9 +66,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,

7
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View file

@ -27,21 +27,14 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY"
register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

10
src/mainboard/google/hatch/variants/nightfury/overridetree.cb
View file

@ -27,21 +27,11 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_EMPTY"
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_EMPTY"
register "usb3_ports[3]" = "USB3_PORT_EMPTY"
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

5
src/mainboard/google/hatch/variants/noibat/overridetree.cb
View file

@ -48,7 +48,6 @@ chip soc/intel/cannonlake
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 3
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "{
.enable = 1,
.ocpin = OC0,
@ -57,9 +56,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,
@ -74,7 +70,6 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Type-A Port 4
# Bitmap for Wake Enable on USB attach/detach
register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \

3
src/mainboard/google/hatch/variants/puff/overridetree.cb
View file

@ -63,9 +63,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,

8
src/mainboard/google/hatch/variants/stryke/overridetree.cb
View file

@ -18,20 +18,12 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_EMPTY"
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" #Front Camera
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0
register "usb3_ports[3]" = "USB3_PORT_EMPTY"
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

3
src/mainboard/google/hatch/variants/wyvern/overridetree.cb
View file

@ -60,9 +60,6 @@ chip soc/intel/cannonlake
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A port 0
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "{
.enable = 1,
.ocpin = OC_SKIP,

5
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file

@ -149,17 +149,12 @@ chip soc/intel/skylake
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Empty
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
# USB 3.0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -148,7 +148,6 @@ chip soc/intel/skylake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

5
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View file

@ -159,18 +159,13 @@ chip soc/intel/skylake
# USB 2.0
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty
register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth
register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # pogo port
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Empty
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty
# USB 3.0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View file

@ -153,7 +153,6 @@ chip soc/intel/skylake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -148,7 +148,6 @@ chip soc/intel/skylake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# Intel Common SoC Config
#+-------------------+---------------------------+

4
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View file

@ -132,8 +132,6 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[6]" = "{
.enable = 1, \
@ -151,8 +149,6 @@ chip soc/intel/cannonlake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

2
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View file

@ -139,7 +139,6 @@ chip soc/intel/cannonlake
register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1
register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port
register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH
@ -151,7 +150,6 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+

3
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View file

@ -55,9 +55,6 @@ chip soc/intel/tigerlake
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth

10
src/mainboard/google/volteer/variants/halvor/overridetree.cb
View file

@ -1,20 +1,10 @@
chip soc/intel/tigerlake
register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 0
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT
register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 2
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"
device domain 0 on

8
src/mainboard/google/volteer/variants/lindar/overridetree.cb
View file

@ -1,20 +1,12 @@
chip soc/intel/tigerlake
# USB Port Config
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"
# I2C Port Config

8
src/mainboard/google/volteer/variants/malefor/overridetree.cb
View file

@ -2,20 +2,12 @@ chip soc/intel/tigerlake
# USB Port Config
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C C0
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"

3
src/mainboard/google/volteer/variants/terrador/overridetree.cb
View file

@ -10,12 +10,9 @@ chip soc/intel/tigerlake
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"

3
src/mainboard/google/volteer/variants/todor/overridetree.cb
View file

@ -10,12 +10,9 @@ chip soc/intel/tigerlake
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled"

3
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View file

@ -14,9 +14,6 @@ chip soc/intel/cannonlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
View file

@ -15,12 +15,10 @@ chip soc/intel/cannonlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[13]" = "USB2_PORT_EMPTY"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"

2
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View file

@ -93,8 +93,6 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SsicPortEnable" = "1" # Enable SSIC for WWAN

2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View file

@ -29,8 +29,6 @@ chip soc/intel/tigerlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View file

@ -22,14 +22,10 @@ chip soc/intel/tigerlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
# CPU replacement check

2
src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
View file

@ -118,8 +118,6 @@ chip soc/intel/cannonlake
# USB OC5-7: not connected
# BMC
register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)"
# unused
register "usb2_ports[11]" = "USB2_PORT_EMPTY"
# piggy-back
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
# M2 key E

6
src/mainboard/protectli/vault_kbl/devicetree.cb
View file

@ -177,18 +177,12 @@ chip soc/intel/skylake
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # mPCIe slot
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disabled
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disabled
# USB 3.0 enable ports 1-4, disable ports 5-6
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoDisabled, \

13
src/mainboard/purism/librem_whl/devicetree.cb
View file

@ -82,27 +82,14 @@ chip soc/intel/cannonlake
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
# All SRCCLKREQ pins mapped directly
register "PcieClkSrcClkReq[0]" = "0"

30
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View file

@ -39,36 +39,6 @@ chip soc/intel/skylake
# superspeed_inter-chip_supplement (SSIC) disabled
register "SsicPortEnable" = "0"
# USB
register "usb2_ports" = "{
[0] = USB2_PORT_EMPTY,
[1] = USB2_PORT_EMPTY,
[2] = USB2_PORT_EMPTY,
[3] = USB2_PORT_EMPTY,
[4] = USB2_PORT_EMPTY,
[5] = USB2_PORT_EMPTY,
[6] = USB2_PORT_EMPTY,
[7] = USB2_PORT_EMPTY,
[8] = USB2_PORT_EMPTY,
[9] = USB2_PORT_EMPTY,
[10] = USB2_PORT_EMPTY,
[11] = USB2_PORT_EMPTY,
[12] = USB2_PORT_EMPTY,
[13] = USB2_PORT_EMPTY,
}"
register "usb3_ports" = "{
[0] = USB3_PORT_EMPTY,
[1] = USB3_PORT_EMPTY,
[2] = USB3_PORT_EMPTY,
[3] = USB3_PORT_EMPTY,
[4] = USB3_PORT_EMPTY,
[5] = USB3_PORT_EMPTY,
[6] = USB3_PORT_EMPTY,
[7] = USB3_PORT_EMPTY,
[8] = USB3_PORT_EMPTY,
[9] = USB3_PORT_EMPTY,
}"
# LPC
register "serirq_mode" = "SERIRQ_CONTINUOUS"