soc/intel/jasperlakelake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=Able to build and boot Waddledoo successfully. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Iaa0a41f3b5972251d6cd9359bbb46d392196b2e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -25,7 +25,7 @@ void bootblock_soc_early_init(void)
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void bootblock_soc_init(void)
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{
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report_platform_info();
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pch_init();
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bootblock_pch_init();
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/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
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tco_configure();
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@ -142,7 +142,7 @@ void pch_early_iorange_init(void)
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pch_enable_lpc();
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}
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void pch_init(void)
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void bootblock_pch_init(void)
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{
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/*
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* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
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@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
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void bootblock_pch_early_init(void);
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/* Bootblock post console init programming */
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void pch_init(void);
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void bootblock_pch_init(void);
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void pch_early_iorange_init(void);
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void report_platform_info(void);
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@ -9,7 +9,7 @@
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bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
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void mainboard_memory_init_params(FSPM_UPD *mupd);
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void systemagent_early_init(void);
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void pch_init(void);
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void romstage_pch_init(void);
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/* Board type */
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enum board_type {
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@ -3,7 +3,7 @@
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#include <intelblocks/smbus.h>
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#include <soc/romstage.h>
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void pch_init(void)
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void romstage_pch_init(void)
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{
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/* Program SMBUS_BASE_ADDRESS and Enable it */
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smbus_common_init();
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@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
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/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
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systemagent_early_init();
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/* Program PCH init */
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pch_init();
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romstage_pch_init();
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/* initialize Heci interface */
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heci_init(HECI1_BASE_ADDRESS);
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