diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
index 99536d4dfd..d8df39b455 100644
--- a/src/arch/x86/include/arch/ioapic.h
+++ b/src/arch/x86/include/arch/ioapic.h
@@ -32,7 +32,6 @@ void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
 u8 get_ioapic_id(void *ioapic_base);
 u8 get_ioapic_version(void *ioapic_base);
 void setup_ioapic(void *ioapic_base, u8 ioapic_id);
-void clear_ioapic(void *ioapic_base);
 
 void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb);
 #endif
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
index 61fed890d1..1d30baad48 100644
--- a/src/arch/x86/ioapic.c
+++ b/src/arch/x86/ioapic.c
@@ -60,11 +60,6 @@ static void clear_vectors(void *ioapic_base, u8 first, u8 last)
 	}
 }
 
-void clear_ioapic(void *ioapic_base)
-{
-	clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
-}
-
 static void route_i8259_irq0(void *ioapic_base)
 {
 	u32 bsp_lapicid = lapicid();
@@ -139,6 +134,6 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
 void setup_ioapic(void *ioapic_base, u8 ioapic_id)
 {
 	set_ioapic_id(ioapic_base, ioapic_id);
-	clear_ioapic(ioapic_base);
+	clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
 	route_i8259_irq0(ioapic_base);
 }
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 9fdf596cbd..b6cc3c777b 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -340,7 +340,6 @@ static void sb800_enable(struct device *dev)
 		break;
 
 	case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */
-		clear_ioapic(VIO_APIC_VADDR);
 		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
 		setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 		break;