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security/intel/txt: Fix GETSEC checks in romstage 

IA32_FEATURE_CONTROL does not need to be checked by BIOS, in fact these
bits are needed only by SENTER and SINIT ACM. ACM ENTERACCS does not
check these bits according to Intel SDM. Also noticed that the lock bit
of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global
reset nor full reset on Sandybridge/Ivybridge platforms which results
in a reset loop. However, check the IA32_FEATURE_CONTROL SENTER bits in
ramstage where the register is properly set on all cores already.

TEST=Run ACM SCLEAN on Dell OptiPlex 9010 with i7-3770/Q77

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Michał Żygowski 2021-11-21 13:13:15 +01:00
parent 50449eb05f
commit 257094ac1a
2 changed files with 31 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/security/intel/txt/getsec.c
View File

@ -9,6 +9,7 @@
#include <cpu/x86/mp.h> #include <cpu/x86/mp.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <types.h> #include <types.h>
#include <rules.h>
#include "txt_register.h" #include "txt_register.h"
#include "txt_getsec.h" #include "txt_getsec.h"
@ -24,16 +25,26 @@ static bool getsec_enabled(void)
/* /*
* Check if SMX and VMX is supported by CPU. * Check if SMX and VMX is supported by CPU.
*/ */
if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) if (!(ecx & CPUID_SMX) || !(ecx & CPUID_VMX)) {
printk(BIOS_ERR, "SMX/VMX not supported by CPU\n");
return false; return false;
}
/* /*
* Check if SMX, VMX and GetSec instructions haven't been disabled. * This requirement is not needed for ENTERACCS, but for SENTER (see SDM).
* Skip check in romstage because IA32_FEATURE_CONTROL cannot be unlocked
* even after a global reset e.g. on Sandy/IvyBridge. However the register
* gets set properly in ramstage where all CPUs are already initialized.
*/ */
msr_t msr = rdmsr(IA32_FEATURE_CONTROL); if (!ENV_ROMSTAGE_OR_BEFORE) {
if ((msr.lo & 0xff06) != 0xff06) /*
return false; * Check if SMX, VMX and GetSec instructions haven't been disabled.
*/
msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if ((msr.lo & 0xff06) != 0xff06) {
printk(BIOS_ERR, "GETSEC not enabled in IA32_FEATURE_CONTROL MSR\n");
return false;
}
}
/* /*
* Enable SMX. Required to execute GetSec instruction. * Enable SMX. Required to execute GetSec instruction.
* Chapter 2.2.4.3 * Chapter 2.2.4.3

17
src/security/intel/txt/romstage.c
View File

@ -5,6 +5,7 @@
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/common/common.h> #include <cpu/intel/common/common.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmbase.h>
#include <timer.h> #include <timer.h>
@ -83,14 +84,22 @@ static void print_memory_is_locked(void)
void intel_txt_romstage_init(void) void intel_txt_romstage_init(void)
{ {
/* Bail early if the CPU doesn't support TXT */ /* Bail early if the CPU doesn't support TXT */
if (!is_txt_cpu()) if (!is_txt_cpu()) {
printk(BIOS_ERR, "TEE-TXT: CPU not TXT capable.\n");
return; return;
}
/* We need to use GETSEC here, so enable it */ /*
enable_getsec_or_reset(); * We need to use GETSEC here, so enable it.
* CR4_SMXE is all we need to be able to call GETSEC[CAPABILITIES]
* or GETSEC[ENTERACCS] for SCLEAN.
*/
write_cr4(read_cr4() | CR4_SMXE);
if (!is_txt_chipset()) if (!is_txt_chipset()) {
printk(BIOS_ERR, "TEE-TXT: Chipset not TXT capable.\n");
return; return;
}
const uint8_t txt_ests = read8((void *)TXT_ESTS); const uint8_t txt_ests = read8((void *)TXT_ESTS);