mb/lenovo/t530/*/*/devicetree: Align whitespace and comments across the boards
Only whitespace changes, minor comments. This helps making diff between devicetrees shorter. Change-Id: Ia1a84728abbece96a3d05b3b1616ac58535845bc Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Peter Lemenkov
Patrick Georgi
parent
e7dd380402
commit
257cc4f9c3
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@ -39,9 +39,9 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x17aa 0x21f6 inherit
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device pci 00.0 on end # host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on end # vga controller
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe bridge for discrete graphics
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device pci 02.0 on end # Internal graphics VGA controller
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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@ -52,7 +52,6 @@ chip northbridge/intel/sandybridge
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register "gpi1_routing" = "2"
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register "gpi13_routing" = "2"
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# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock)
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register "sata_port_map" = "0x3f"
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# Set max SATA speed to 6.0 Gb/s
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register "sata_interface_speed_support" = "0x3"
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@ -69,7 +68,7 @@ chip northbridge/intel/sandybridge
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register "xhci_switchable_ports" = "0xf"
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register "superspeed_capable_ports" = "0xf"
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register "xhci_overcurrent_mapping" = "0x4000201"
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register "xhci_overcurrent_mapping" = "0x04000201"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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@ -86,9 +85,9 @@ chip northbridge/intel/sandybridge
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 on end # PCIe Port #2
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device pci 1c.2 on
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device pci 1c.2 on # PCIe Port #3
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smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
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end # PCIe Port #3 (expresscard)
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end
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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@ -96,10 +95,9 @@ chip northbridge/intel/sandybridge
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on #LPC bridge
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device pci 1f.0 on # PCI-LPC bridge
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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device pnp ff.1 on end # dummy
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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@ -162,9 +160,9 @@ chip northbridge/intel/sandybridge
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register "has_thinker1" = "1"
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end
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end # LPC bridge
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on
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device pci 1f.3 on # SMBus
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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@ -176,7 +174,7 @@ chip northbridge/intel/sandybridge
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device i2c 5e on end
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device i2c 5f on end
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end
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end # SMBus
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end
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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end
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@ -14,31 +14,40 @@ chip northbridge/intel/sandybridge
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register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
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register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
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register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
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register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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device cpu_cluster 0x0 on
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chip cpu/intel/model_206ax # FIXME: check all registers
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0x0 on end
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device lapic 0xacac off end
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register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0x0 on
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device domain 0 on
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subsystemid 0x17aa 0x21f6 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PCIe bridge for discrete graphics
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device pci 02.0 on # Internal graphics VGA controller
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subsystemid 0x17aa 0x21f5
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end
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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@ -48,20 +57,29 @@ chip northbridge/intel/sandybridge
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register "gpi1_routing" = "2"
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register "gpi13_routing" = "2"
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register "c2_latency" = "0x0065"
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register "docking_supported" = "1"
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register "gen1_dec" = "0x007c1601"
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register "gen2_dec" = "0x000c15e1"
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register "gen4_dec" = "0x000c06a1"
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3f"
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# Set max SATA speed to 6.0 Gb/s
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register "sata_interface_speed_support" = "0x3"
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register "gen1_dec" = "0x7c1601"
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register "gen2_dec" = "0x0c15e1"
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register "gen4_dec" = "0x0c06a1"
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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register "c2_latency" = "101" # c2 not supported
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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register "xhci_switchable_ports" = "0xf"
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register "superspeed_capable_ports" = "0xf"
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register "xhci_overcurrent_mapping" = "0x04000201"
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register "docking_supported" = "1"
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register "spi_uvscc" = "0x2005"
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register "spi_lvscc" = "0x2005"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x04000201"
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register "xhci_switchable_ports" = "0x0000000f"
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device pci 14.0 on end # USB 3.0 Controller
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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@ -71,7 +89,7 @@ chip northbridge/intel/sandybridge
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subsystemid 0x17aa 0x21f3
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end
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # High Definition Audio Audio controller
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on # PCIe Port #1
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chip drivers/ricoh/rce822 # Ricoh cardreader
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register "disable_mask" = "0x83"
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@ -90,11 +108,11 @@ chip northbridge/intel/sandybridge
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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device pci 1f.0 on # PCI-LPC bridge
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chip ec/lenovo/pmh7
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device pnp ff.1 on end # dummy
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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device pnp ff.1 on end # dummy
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end
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chip drivers/pc80/tpm
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@ -102,14 +120,23 @@ chip northbridge/intel/sandybridge
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end
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chip ec/lenovo/h8
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa7"
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register "config1" = "0x01"
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register "config2" = "0xa0"
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register "config3" = "0xe2"
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register "has_keyboard_backlight" = "1"
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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register "has_power_management_beeps" = "0"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xd0"
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@ -124,18 +151,9 @@ chip northbridge/intel/sandybridge
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register "eventd_enable" = "0xff"
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register "evente_enable" = "0x0d"
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register "has_keyboard_backlight" = "1"
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register "has_power_management_beeps" = "0"
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register "has_bdc_detection" = "1"
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register "bdc_gpio_num" = "54"
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register "bdc_gpio_lvl" = "0"
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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end
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chip drivers/lenovo/hybrid_graphics
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device pnp ff.f on end # dummy
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@ -154,7 +172,8 @@ chip northbridge/intel/sandybridge
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on # SMBus
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chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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@ -168,10 +187,5 @@ chip northbridge/intel/sandybridge
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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device pci 00.0 on end # Host bridge Host bridge
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device pci 01.0 on end # PCIe Bridge for discrete graphics
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device pci 02.0 on # Internal graphics VGA controller
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subsystemid 0x17aa 0x21f5
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end
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end
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end
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