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mb/siemens/mc_ehl: Disable HS400 mode for eMMC 

In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.

Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Werner Zeh 2022-02-24 06:50:29 +01:00 committed by Felix Held
parent 03575db36a
commit 257e2507fa
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
View File

@ -84,7 +84,7 @@ chip soc/intel/elkhartlake
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"

2
src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
View File

@ -69,7 +69,7 @@ chip soc/intel/elkhartlake
register "PcieRpLtrDisable[6]" = "true"
# Storage (SDCARD/EMMC) related UPDs
register "ScsEmmcHs400Enabled" = "1"
register "ScsEmmcHs400Enabled" = "0"
register "ScsEmmcDdr50Enabled" = "1"
register "SdCardPowerEnableActiveHigh" = "1"