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mb/intel/jslrvp: Update PMC as hidden device 

This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.

Original patch for jasperlake SoC here:
CB:42018

This change was missing for JasperLake rvp board.

TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.

Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Maulik V Vaghela 2020-09-28 19:36:56 +05:30 committed by Subrata Banik
parent 823e73e143
commit 258ceb7507
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
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@ -466,7 +466,7 @@ chip soc/intel/jasperlake
end # GSPI #1 end # GSPI #1
device pci 1f.0 on end # eSPI Interface device pci 1f.0 on end # eSPI Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on end # Intel HDA device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI device pci 1f.5 on end # PCH SPI