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soc/mediatek/mt8183: Do TX tracking for DRAM DVFS feature 

The TX window will offset to edge during DVFS switch, which may cause
TX data transmission error and random kernel crash. Therefore, use the
standard dqsosc (DQS Oscillator) for TX window tracking.

BUG=b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Huayang Duan 2019-12-30 13:19:05 +08:00 committed by Patrick Georgi
parent 998737df71
commit 25930f4a3f
5 changed files with 776 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/mediatek/mt8183/dramc_pi_basic_api.c
View File

@ -427,6 +427,9 @@ void dramc_runtime_config(void)
transfer_pll_to_spm_control(); transfer_pll_to_spm_control();
setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
dramc_hw_dqsosc(chn);
/* RX_TRACKING: ON */ /* RX_TRACKING: ON */
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
dramc_rx_input_delay_tracking(chn); dramc_rx_input_delay_tracking(chn);
@ -498,6 +501,7 @@ void dramc_runtime_config(void)
(0x3 << 4) | (0x1 << 2) | (0x1 << 0)); (0x3 << 4) | (0x1 << 2) | (0x1 << 0));
setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
} }
dramc_dqs_precalculation_preset();
enable_emi_dcm(); enable_emi_dcm();
dramc_enable_dramc_dcm(); dramc_enable_dramc_dcm();

620
src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
View File

@ -105,6 +105,25 @@ void dramc_cke_fix_onoff(u8 chn, bool cke_on, bool cke_off)
CKECTRL_CKEFIXOFF, cke_off); CKECTRL_CKEFIXOFF, cke_off);
} }
static u16 dramc_mode_reg_read(u8 chn, u8 mr_idx)
{
u16 value;
SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx);
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 1);
/* Wait until MRW command fired */
while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE)
== 0)
udelay(1);
value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_REG);
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRREN, 0);
dramc_dbg("Read MR%d =%#x\n", mr_idx, value);
return value;
}
void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
{ {
u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl);
@ -117,7 +136,7 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value)
/* Wait MRW command fired */ /* Wait MRW command fired */
while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE) while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRW_RESPONSE)
== 0) == 0)
; udelay(1);
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0); SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0);
write32(&ch[chn].ao.ckectrl, ckectrl_bak); write32(&ch[chn].ao.ckectrl, ckectrl_bak);
@ -1577,17 +1596,9 @@ static void dramc_set_tx_dly_center(struct per_byte_dly *center_dly,
} }
} }
static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx, static u32 get_freq_group_clock(u8 freq_group)
struct win_perbit_dly *vref_dly, enum CAL_TYPE type, u8 freq_group,
u16 *tx_dq_precal_result, u16 dly_cell_unit, const struct sdram_params *params,
const bool fast_calib)
{ {
int index, clock_rate; u32 clock_rate = 0;
u8 use_delay_cell;
u32 byte_dly_cell[DQS_NUMBER] = {0};
struct per_byte_dly center_dly[DQS_NUMBER];
u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];
/* /*
* The clock rate is usually (frequency / 2 - delta), where the delta * The clock rate is usually (frequency / 2 - delta), where the delta
@ -1609,9 +1620,27 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx,
break; break;
default: default:
die("Invalid DDR frequency group %u\n", freq_group); die("Invalid DDR frequency group %u\n", freq_group);
return; break;
} }
return clock_rate;
}
static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx,
struct win_perbit_dly *vref_dly,
enum CAL_TYPE type, u8 freq_group,
u16 *tx_dq_precal_result, u16 dly_cell_unit,
const struct sdram_params *params,
const bool fast_calib)
{
int index, clock_rate;
u8 use_delay_cell;
u32 byte_dly_cell[DQS_NUMBER] = { 0 };
struct per_byte_dly center_dly[DQS_NUMBER];
u16 tune_diff, dq_delay_cell[DQ_DATA_WIDTH];
clock_rate = get_freq_group_clock(freq_group);
if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1) if (type == TX_WIN_DQ_ONLY && get_freq_fsq(freq_group) == FSP_1)
use_delay_cell = 1; use_delay_cell = 1;
else else
@ -1653,7 +1682,7 @@ static void dramc_set_tx_best_dly(u8 chn, u8 rank, bool bypass_tx,
dq_delay_cell[index] = ((tune_diff * 100000000) / dq_delay_cell[index] = ((tune_diff * 100000000) /
(clock_rate * 64)) / dly_cell_unit; (clock_rate * 64)) / dly_cell_unit;
byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4)); byte_dly_cell[byte] |= (dq_delay_cell[index] << (bit * 4));
dramc_show("u1DelayCellOfst[%d]=%d cells (%d PI)\n", dramc_dbg("u1DelayCellOfst[%d]=%d cells (%d PI)\n",
index, dq_delay_cell[index], tune_diff); index, dq_delay_cell[index], tune_diff);
} }
} }
@ -2104,6 +2133,566 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
(0xff << 8) | (0x9 << 2) | ROEN); (0xff << 8) | (0x9 << 2) | ROEN);
} }
static void start_dqsosc(u8 chn)
{
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 1);
if (!wait_us(100, READ32_BITFIELD(&ch[chn].nao.spcmdresp,
SPCMDRESP_DQSOSCEN_RESPONSE))) {
dramc_err("start dqsosc timed out\n");
return;
}
SET32_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSOSCENEN, 0);
}
static void dqsosc_auto(u8 chn, u8 rank, u8 freq_group,
u16 *osc_thrd_inc, u16 *osc_thrd_dec)
{
u8 mr23 = MR23_DEFAULT_VALUE;
u16 mr18, mr19;
u16 dqsosc_cnt[2], dqs_cnt, dqsosc, thrd_inc, thrd_dec;
u32 clock_rate, tck;
struct reg_value regs_bak[] = {
{&ch[chn].ao.mrs},
{&ch[chn].ao.dramc_pd_ctrl},
{&ch[chn].ao.ckectrl},
};
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
regs_bak[i].value = read32(regs_bak[i].addr);
SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_DQSOSC2RK, 0);
SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
dramc_mode_reg_write(chn, 23, mr23);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv,
SHU_SCINTV_DQSOSCENDIS, 1);
SET32_BITFIELDS(&ch[chn].ao.dramc_pd_ctrl,
DRAMC_PD_CTRL_MIOCKCTRLOFF, 1);
dramc_cke_fix_onoff(chn, true, false);
start_dqsosc(chn);
udelay(1);
SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank);
mr18 = dramc_mode_reg_read(chn, 18);
mr19 = dramc_mode_reg_read(chn, 19);
dqsosc_cnt[0] = (mr18 & 0xff) | ((mr19 & 0xff) << 8);
dqsosc_cnt[1] = (mr18 >> 8) | (mr19 & 0xff00);
dramc_dbg("DQSOscCnt B0=%#x, B1=%#x\n", dqsosc_cnt[0], dqsosc_cnt[1]);
/* get the INC and DEC values */
clock_rate = get_freq_group_clock(freq_group);
tck = 1000000 / clock_rate;
dqs_cnt = (mr18 & 0xff) | ((mr19 & 0xff) << 8);
if (dqs_cnt != 0) {
dqsosc = mr23 * 16 * 1000000 / (2 * dqs_cnt * clock_rate);
thrd_inc = mr23 * tck * tck / (dqsosc * dqsosc * 10);
thrd_dec = 3 * mr23 * tck * tck / (dqsosc * dqsosc * 20);
} else {
dqsosc = 0;
thrd_inc = 0x6;
thrd_dec = 0x4;
}
osc_thrd_inc[rank] = thrd_inc;
osc_thrd_dec[rank] = thrd_dec;
dramc_dbg("CH%d_RK%d: MR18=%#x, MR19=%#x, DQSOSC=%d, MR23=%d, "
"INC=%d, DEC=%d\n",
chn, rank, mr18, mr19, dqsosc, mr23, thrd_inc, thrd_dec);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
write32(regs_bak[i].addr, regs_bak[i].value);
SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[rank].dqsosc,
SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, dqsosc_cnt[0],
SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, dqsosc_cnt[1]);
}
void dramc_hw_dqsosc(u8 chn)
{
u32 freq_shu1 = get_shu_freq(DRAM_DFS_SHUFFLE_1);
u32 freq_shu2 = get_shu_freq(DRAM_DFS_SHUFFLE_2);
u32 freq_shu3 = get_shu_freq(DRAM_DFS_SHUFFLE_3);
SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc,
RK2_DQSOSC_FREQ_RATIO_TX_0, freq_shu2 * 8 / freq_shu1,
RK2_DQSOSC_FREQ_RATIO_TX_1, freq_shu3 * 8 / freq_shu1);
SET32_BITFIELDS(&ch[chn].ao.rk[2].dqsosc,
RK2_DQSOSC_FREQ_RATIO_TX_3, freq_shu1 * 8 / freq_shu2,
RK2_DQSOSC_FREQ_RATIO_TX_4, freq_shu3 * 8 / freq_shu2);
SET32_BITFIELDS(&ch[chn].ao.rk[2].dummy_rd_bk,
RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6,
freq_shu1 * 8 / freq_shu3,
RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7,
freq_shu2 * 8 / freq_shu3);
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0],
PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 1,
PRE_TDQSCK1_SHU_PRELOAD_TX_START, 0,
PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 0);
SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPC_BLOCKALE_OPT, 0);
SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMARPIDQ_SW, 1);
SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_ARUIDQ_SW, 1);
SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 1);
SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc, RK0_DQSOSC_DQSOSCR_RK0EN, 1);
SET32_BITFIELDS(&ch[chn].ao.rk[1].dqsosc, RK1_DQSOSC_DQSOSCR_RK1EN, 1);
SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSC_CALEN, 1);
for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
SET32_BITFIELDS(&ch[chn].ao.shu[shu].scintv,
SHU_SCINTV_DQSOSCENDIS, 1);
}
static void dqsosc_shu_settings(u8 chn, u8 freq_group,
u16 *osc_thrd_inc, u16 *osc_thrd_dec)
{
u8 filt_pithrd, w2r_sel, upd_sel;
u8 mr23 = MR23_DEFAULT_VALUE;
u16 prd_cnt, thrd_inc, thrd_dec;
SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv,
SHU_SCINTV_DQS2DQ_SHU_PITHRD, 0);
SET32_BITFIELDS(&ch[chn].ao.rk[0].dqsosc,
RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 0);
switch (freq_group) {
case LP4X_DDR1600:
filt_pithrd = 0x5;
w2r_sel = 0x5;
upd_sel = 0x0;
break;
case LP4X_DDR2400:
filt_pithrd = 0x8;
w2r_sel = 0x2;
upd_sel = 0x0;
break;
case LP4X_DDR3200:
filt_pithrd = 0xA;
w2r_sel = 0x2;
upd_sel = 0x0;
break;
case LP4X_DDR3600:
filt_pithrd = 0xB;
w2r_sel = 0x2;
upd_sel = 0x0;
break;
default:
die("Invalid DDR frequency group %u\n", freq_group);
return;
}
SET32_BITFIELDS(&ch[chn].ao.shu[0].scintv,
SHU_SCINTV_DQS2DQ_FILT_PITHRD, filt_pithrd);
SET32_BITFIELDS(&ch[chn].ao.shu[0].wodt,
SHU1_WODT_TXUPD_W2R_SEL, w2r_sel,
SHU1_WODT_TXUPD_SEL, upd_sel);
prd_cnt = mr23 / 4 + 3;
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd,
SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, prd_cnt);
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr,
SHU_DQSOSCR_DQSOSCRCNT, 0x40);
for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
thrd_inc = osc_thrd_inc[rk];
thrd_dec = osc_thrd_dec[rk];
if (rk == RANK_0) {
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0,
thrd_inc);
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0,
thrd_dec);
} else {
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscthrd,
SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0,
thrd_inc & 0xFF);
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd,
SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8,
(thrd_inc & 0xF00) >> 8);
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsosc_prd,
SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1,
thrd_dec);
}
}
SET32_BITFIELDS(&ch[chn].ao.shu[0].dqsoscr2,
SHU_DQSOSCR2_DQSOSCENCNT, 0x1FF);
}
void dramc_dqs_precalculation_preset(void)
{
u32 jump_ratio_index = 0;
u16 jump_ratio[DRAM_DFS_SHUFFLE_MAX * HW_REG_SHUFFLE_MAX] = {0};
u32 u4value = 0, u4value1 = 0;
for (u8 shu_src = 0; shu_src < HW_REG_SHUFFLE_MAX; shu_src++)
for (u8 shu_dst = 0; shu_dst < HW_REG_SHUFFLE_MAX; shu_dst++) {
if (shu_src == shu_dst)
continue;
if (shu_src >= DRAM_DFS_SHUFFLE_MAX ||
shu_dst >= DRAM_DFS_SHUFFLE_MAX) {
jump_ratio_index++;
continue;
}
jump_ratio[jump_ratio_index] = DIV_ROUND_CLOSEST(
(get_shu_freq(shu_dst) >> 1) * 32,
get_shu_freq(shu_src) >> 1);
dramc_dbg("Jump_RATIO [%d]: %x Freq %d -> %d DDR%d ->"
" DDR%d\n",
jump_ratio_index,
jump_ratio[jump_ratio_index],
shu_src + 1, shu_dst + 1,
get_shu_freq(shu_src), get_shu_freq(shu_dst));
jump_ratio_index++;
}
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
struct dramc_ao_regs_shu *shu = &ch[chn].ao.shu[0];
struct dramc_ao_regs_rk *rk = &ch[chn].ao.rk[0];
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0],
PRE_TDQSCK1_TDQSCK_PRECAL_HW, 1);
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[1],
PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, jump_ratio[0],
PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, jump_ratio[1],
PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, jump_ratio[2],
PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, jump_ratio[3]);
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[2],
PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, jump_ratio[4],
PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, jump_ratio[5],
PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, jump_ratio[6],
PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, jump_ratio[7]);
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[3],
PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, jump_ratio[8],
PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, jump_ratio[9],
PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, jump_ratio[10],
PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, jump_ratio[11]);
for (u8 rnk = RANK_0; rnk < RANK_MAX; rnk++) {
/* Shuffle 0 */
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0],
RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS0IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0],
RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0,
u4value);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2],
RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0,
(u4value << 3) | u4value1);
/* Shuffle 1 */
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0],
RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS0IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[0],
RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, u4value);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2],
RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0,
(u4value << 3) | u4value1);
/* Shuffle 2 */
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[1],
RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS0IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[1],
RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0,
u4value);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[2],
RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0,
(u4value << 3) | u4value1);
/* Byte 1 */
/* Shuffle 0 */
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3],
RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS1IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3],
RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0,
u4value);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5],
RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0,
(u4value << 3) | u4value1);
/* Shuffle 1 */
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3],
RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS1IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[3],
RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0,
u4value);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5],
RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0,
(u4value << 3) | u4value1);
/* Shuffle 2 */
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[4],
RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS1IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[4],
RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0,
u4value);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[5],
RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0,
(u4value << 3) | u4value1);
/* Byte 2 */
/* Shuffle 0 */
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6],
RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS2IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6],
RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0,
u4value);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8],
RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0,
(u4value << 3) | u4value1);
/* Shuffle 1 */
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6],
RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS2IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[6],
RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0,
u4value);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8],
RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0,
(u4value << 3) | u4value1);
/* Shuffle 2 */
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[7],
RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS2IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[7],
RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0,
u4value);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[8],
RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0,
(u4value << 3) | u4value1);
/* Byte 3 */
/* Shuffle 0 */
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9],
RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS3IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9],
RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0,
u4value);
u4value = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[0].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11],
RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0,
(u4value << 3) | u4value1);
/* Shuffle 1 */
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9],
RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS3IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[9],
RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0,
u4value);
u4value = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[1].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11],
RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0,
(u4value << 3) | u4value1);
/* Shuffle 2 */
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[10],
RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0,
(u4value << 3) | u4value1);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].dqsien,
SHURK0_DQSIEN_R0DQS3IEN);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[10],
RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0,
u4value);
u4value = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg0,
SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1);
u4value1 = READ32_BITFIELD(
&shu[2].rk[rnk].selph_dqsg1,
SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1);
SET32_BITFIELDS(&rk[rnk].pre_tdqsck[11],
RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0,
(u4value << 3) | u4value1);
}
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0],
PRE_TDQSCK1_TDQSCK_REG_DVFS, 0x1);
SET32_BITFIELDS(&ch[chn].ao.pre_tdqsck[0],
PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 1);
}
}
int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
const struct mr_value *mr) const struct mr_value *mr)
{ {
@ -2122,6 +2711,8 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
bool test_passed; bool test_passed;
u8 rx_datlat[RANK_MAX] = {0}; u8 rx_datlat[RANK_MAX] = {0};
u16 osc_thrd_inc[RANK_MAX];
u16 osc_thrd_dec[RANK_MAX];
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n",
@ -2146,8 +2737,11 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group,
dramc_window_perbit_cal(chn, rk, freq_group, dramc_window_perbit_cal(chn, rk, freq_group,
RX_WIN_TEST_ENG, pams, fast_calib); RX_WIN_TEST_ENG, pams, fast_calib);
dramc_auto_refresh_switch(chn, false); dramc_auto_refresh_switch(chn, false);
dqsosc_auto(chn, rk, freq_group, osc_thrd_inc, osc_thrd_dec);
} }
dqsosc_shu_settings(chn, freq_group, osc_thrd_inc, osc_thrd_dec);
dramc_rx_dqs_gating_post_process(chn, freq_group); dramc_rx_dqs_gating_post_process(chn, freq_group);
dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]); dramc_dual_rank_rx_datlat_cal(chn, freq_group, rx_datlat[0], rx_datlat[1]);
} }

9
src/soc/mediatek/mt8183/emi.c
View File

@ -34,7 +34,7 @@ static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = {
[DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600,
}; };
u32 frequency_table[LP4X_DDRFREQ_MAX] = { static const u32 frequency_table[LP4X_DDRFREQ_MAX] = {
[LP4X_DDR1600] = 1600, [LP4X_DDR1600] = 1600,
[LP4X_DDR2400] = 2400, [LP4X_DDR2400] = 2400,
[LP4X_DDR3200] = 3200, [LP4X_DDR3200] = 3200,
@ -77,6 +77,13 @@ u32 dramc_get_broadcast(void)
return read32(&mt8183_infracfg->dramc_wbr); return read32(&mt8183_infracfg->dramc_wbr);
} }
u32 get_shu_freq(u8 shu)
{
const u8 *freq_tbl = CONFIG(MT8183_DRAM_EMCP) ?
freq_shuffle_emcp : freq_shuffle;
return frequency_table[freq_tbl[shu]];
}
static u64 get_ch_rank_size(u8 chn, u8 rank) static u64 get_ch_rank_size(u8 chn, u8 rank)
{ {
u32 shift_for_16bit = 1; u32 shift_for_16bit = 1;

5
src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
View File

@ -29,6 +29,7 @@
#endif #endif
#define DATLAT_TAP_NUMBER 32 #define DATLAT_TAP_NUMBER 32
#define HW_REG_SHUFFLE_MAX 4
#define DRAMC_BROADCAST_ON 0x1f #define DRAMC_BROADCAST_ON 0x1f
#define DRAMC_BROADCAST_OFF 0x0 #define DRAMC_BROADCAST_OFF 0x0
@ -38,6 +39,7 @@
#define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a #define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a
#define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 #define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16
#define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a #define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a
#define MR23_DEFAULT_VALUE 0x3f
enum dram_te_op { enum dram_te_op {
TE_OP_WRITE_READ_CHECK = 0, TE_OP_WRITE_READ_CHECK = 0,
@ -114,5 +116,8 @@ void dramc_hw_gating_onoff(u8 chn, bool onoff);
void dramc_enable_phy_dcm(bool bEn); void dramc_enable_phy_dcm(bool bEn);
void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);
void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off); void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off);
u32 get_shu_freq(u8 shu);
void dramc_hw_dqsosc(u8 chn);
void dramc_dqs_precalculation_preset(void);
#endif /* _DRAMC_PI_API_MT8183_H */ #endif /* _DRAMC_PI_API_MT8183_H */

152
src/soc/mediatek/mt8183/include/soc/dramc_register.h
View File

@ -627,12 +627,18 @@ check_member(emi_mpu_regs, mpu_ctrl, 0x0000);
check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800); check_member(emi_mpu_regs, mpu_ctrl_d[0], 0x0800);
DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24) DEFINE_BITFIELD(MISC_STATUSA_REFRESH_QUEUE_CNT, 27, 24)
DEFINE_BIT(SPCMDRESP_DQSOSCEN_RESPONSE, 10)
DEFINE_BIT(SPCMDRESP_MRR_RESPONSE, 1)
DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0) DEFINE_BIT(SPCMDRESP_MRW_RESPONSE, 0)
DEFINE_BITFIELD(MRR_STATUS_MRR_REG, 15, 0)
DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22) DEFINE_BIT(DDRCONF0_DM4TO1MODE, 22)
DEFINE_BIT(DDRCONF0_RDATRST, 0) DEFINE_BIT(DDRCONF0_RDATRST, 0)
DEFINE_BIT(PERFCTL0_RWOFOEN, 4) DEFINE_BIT(PERFCTL0_RWOFOEN, 4)
DEFINE_BIT(RKCFG_DQSOSC2RK, 11)
DEFINE_BIT(DRAMC_PD_CTRL_MIOCKCTRLOFF, 26)
DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3) DEFINE_BIT(PADCTRL_DQIENLATEBEGIN, 3)
DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0) DEFINE_BITFIELD(PADCTRL_DQIENQKEND, 1, 0)
@ -655,16 +661,19 @@ DEFINE_BITFIELD(MRS_MRSBA, 23, 21)
DEFINE_BITFIELD(MRS_MRSMA, 20, 8) DEFINE_BITFIELD(MRS_MRSMA, 20, 8)
DEFINE_BITFIELD(MRS_MRSOP, 7, 0) DEFINE_BITFIELD(MRS_MRSOP, 7, 0)
DEFINE_BIT(SPCMD_DQSOSCENEN, 10)
DEFINE_BIT(SPCMD_DQSGCNTRST, 9) DEFINE_BIT(SPCMD_DQSGCNTRST, 9)
DEFINE_BIT(SPCMD_DQSGCNTEN, 8) DEFINE_BIT(SPCMD_DQSGCNTEN, 8)
DEFINE_BIT(SPCMD_ZQLATEN, 6) DEFINE_BIT(SPCMD_ZQLATEN, 6)
DEFINE_BIT(SPCMD_RDDQCEN, 7) DEFINE_BIT(SPCMD_RDDQCEN, 7)
DEFINE_BIT(SPCMD_ZQCEN, 4) DEFINE_BIT(SPCMD_ZQCEN, 4)
DEFINE_BIT(SPCMD_MRREN, 1)
DEFINE_BIT(SPCMD_MRWEN, 0) DEFINE_BIT(SPCMD_MRWEN, 0)
DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11) DEFINE_BIT(SPCMDCTRL_RDDQCDIS, 11)
DEFINE_BIT(MPC_OPTION_MPCRKEN, 17) DEFINE_BIT(MPC_OPTION_MPCRKEN, 17)
DEFINE_BIT(MPC_OPTION_MPC_BLOCKALE_OPT, 0)
DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1) DEFINE_BIT(DVFSDLL_R_BYPASS_1ST_DLL_SHU1, 1)
@ -727,7 +736,39 @@ DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL_ROOT1, 27, 24)
DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20) DEFINE_BITFIELD(SHU_RANKCTL_RANKINCTL, 23, 20)
DEFINE_BIT(SHU1_WODT_DBIWR, 29) DEFINE_BIT(SHU1_WODT_DBIWR, 29)
DEFINE_BIT(SHU_SCINTV_DQSOSCENDIS, 30)
DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_SHU_PITHRD, 23, 18)
DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0) DEFINE_BITFIELD(SHURK_DQSCTL_DQSINCTL, 3, 0)
DEFINE_BIT(RK0_DQSOSC_R_DMDQS2DQ_FILT_OPT, 29)
DEFINE_BIT(RK0_DQSOSC_DQSOSCR_RK0EN, 30)
DEFINE_BIT(RK1_DQSOSC_DQSOSCR_RK1EN, 30)
DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_0, 4, 0)
DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_1, 9, 5)
DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_3, 19, 15)
DEFINE_BITFIELD(RK2_DQSOSC_FREQ_RATIO_TX_4, 24, 20)
DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_6, 7, 3)
DEFINE_BITFIELD(RK2_DUMMY_RD_BK_FREQ_RATIO_TX_7, 12, 8)
DEFINE_BIT(PRE_TDQSCK1_SW_UP_TX_NOW_CASE, 16)
DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_START, 18)
DEFINE_BIT(PRE_TDQSCK1_SHU_PRELOAD_TX_HW, 19)
DEFINE_BITFIELD(SHU_SCINTV_DQS2DQ_FILT_PITHRD, 29, 24)
DEFINE_BITFIELD(SHU1_WODT_TXUPD_W2R_SEL, 16, 14)
DEFINE_BITFIELD(SHU1_WODT_TXUPD_SEL, 13, 12)
DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSC_PRDCNT, 9, 0)
DEFINE_BITFIELD(SHU_DQSOSCR_DQSOSCRCNT, 7, 0)
DEFINE_BIT(DQSOSCR_ARUIDQ_SW, 7)
DEFINE_BIT(DQSOSCR_DQSOSCRDIS, 24)
DEFINE_BIT(DQSOSCR_DQSOSC_CALEN, 31)
DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK0, 11, 0)
DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_DEC_RK0, 23, 12)
DEFINE_BITFIELD(SHU_DQSOSCTHRD_DQSOSCTHRD_INC_RK1_7TO0, 31, 24)
DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_INC_RK1_11TO8, 19, 16)
DEFINE_BITFIELD(SHU1_DQSOSC_PRD_DQSOSCTHRD_DEC_RK1, 31, 20)
DEFINE_BITFIELD(SHU_DQSOSCR2_DQSOSCENCNT, 8, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4) DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
@ -736,6 +777,8 @@ DEFINE_BITFIELD(SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0)
DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS1_GATED_P1, 14, 12)
DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED_P1, 6, 4)
DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0) DEFINE_BITFIELD(SHURK_SELPH_DQSG1_TX_DLY_DQS0_GATED, 2, 0)
DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0, 15, 0)
DEFINE_BITFIELD(SHU1RK0_DQSOSC_DQSOSC_BASE_RK0_B1, 31, 16)
DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16) DEFINE_BIT(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16)
DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16) DEFINE_BIT(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16)
@ -769,6 +812,115 @@ DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CLK, 29, 24)
DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CMD, 13, 8)
DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0) DEFINE_BITFIELD(SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK1) */
DEFINE_BIT(PRE_TDQSCK1_TDQSCK_HW_SW_UP_SEL, 22)
DEFINE_BIT(PRE_TDQSCK1_TDQSCK_REG_DVFS, 25)
DEFINE_BIT(PRE_TDQSCK1_TDQSCK_PRECAL_HW, 26)
/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK2) */
DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO3, 7, 0)
DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO2, 15, 8)
DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO1, 23, 16)
DEFINE_BITFIELD(PRE_TDQSCK2_TDDQSCK_JUMP_RATIO0, 31, 24)
/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK3) */
DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO7, 7, 0)
DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO6, 15, 8)
DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO5, 23, 16)
DEFINE_BITFIELD(PRE_TDQSCK3_TDDQSCK_JUMP_RATIO4, 31, 24)
/* DRAMC_REG_ADDR(DRAMC_REG_PRE_TDQSCK4) */
DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO11, 7, 0)
DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO10, 15, 8)
DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO9, 23, 16)
DEFINE_BITFIELD(PRE_TDQSCK4_TDDQSCK_JUMP_RATIO8, 31, 24)
/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG0) */
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED_P1, 30, 28)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS3_GATED, 26, 24)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED_P1, 22, 20)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS2_GATED, 18, 16)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1, 14, 12)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS1_GATED, 10, 8)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1, 6, 4)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG0_TX_DLY_DQS0_GATED, 2, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_SELPH_DQSG1) */
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED_P1, 30, 28)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS3_GATED, 26, 24)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED_P1, 22, 20)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS2_GATED, 18, 16)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1, 14, 12)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS1_GATED, 10, 8)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1, 6, 4)
DEFINE_BITFIELD(SHURK0_SELPH_DQSG1_REG_DLY_DQS0_GATED, 2, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK1) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ2_B0R0, 25, 19)
DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ2_B0R0, 18, 13)
DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_PIFREQ1_B0R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK1_TDQSCK_UIFREQ1_B0R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_SHURK0_DQSIEN) */
DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS3IEN, 30, 24)
DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS2IEN, 22, 16)
DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS1IEN, 14, 8)
DEFINE_BITFIELD(SHURK0_DQSIEN_R0DQS0IEN, 6, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK3) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ3_P1_B0R0, 17, 12)
DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ2_P1_B0R0, 11, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK3_TDQSCK_UIFREQ1_P1_B0R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK2) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_PIFREQ3_B0R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK2_TDQSCK_UIFREQ3_B0R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK4) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ2_B1R0, 25, 19)
DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ2_B1R0, 18, 13)
DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_PIFREQ1_B1R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK4_TDQSCK_UIFREQ1_B1R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK6) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ3_P1_B1R0, 17, 12)
DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ2_P1_B1R0, 11, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK6_TDQSCK_UIFREQ1_P1_B1R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK5) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_PIFREQ3_B1R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK5_TDQSCK_UIFREQ3_B1R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK7) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ2_B2R0, 25, 19)
DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ2_B2R0, 18, 13)
DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_PIFREQ1_B2R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK7_TDQSCK_UIFREQ1_B2R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK9) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ3_P1_B2R0, 17, 12)
DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ2_P1_B2R0, 11, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK9_TDQSCK_UIFREQ1_P1_B2R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK8) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_PIFREQ3_B2R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK8_TDQSCK_UIFREQ3_B2R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK10) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ2_B3R0, 25, 19)
DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ2_B3R0, 18, 13)
DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_PIFREQ1_B3R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK10_TDQSCK_UIFREQ1_B3R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK12) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ3_P1_B3R0, 17, 12)
DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ2_P1_B3R0, 11, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK12_TDQSCK_UIFREQ1_P1_B3R0, 5, 0)
/* DRAMC_REG_ADDR(DRAMC_REG_RK0_PRE_TDQSCK11) */
DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_PIFREQ3_B3R0, 12, 6)
DEFINE_BITFIELD(RK0_PRE_TDQSCK11_TDQSCK_UIFREQ3_B3R0, 5, 0)
struct dramc_channel_regs { struct dramc_channel_regs {
union { union {
struct dramc_ddrphy_ao_regs phy; struct dramc_ddrphy_ao_regs phy;