GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rambi: switch MCLK from 19.2Mhz to 25Mhz 

With following settings
    1.Coreboot 25Mhz
    2.Maxim codec configured with MCLK=25Mhz
    2.I2C 400Khz fixed
    4.Including  Enable/Disable SHDN bit when LRCLK starts/Stops
    5.Removed PLL toggle workaround routine.
audio playing is smooth before/after S3, no noise when recording so change
MCLK from 19.2 back to 25Mhz.

BUG=chrome-os-partner:26948
BRANCH=firmware-rambi-5216
TEST=test audio play and record on Rambi, works fine.

Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193881
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7219
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kein Yuan 2014-04-04 15:15:14 -07:00 committed by Marc Jones
parent dd20d5d36c
commit 25ae602d2e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/rambi/devicetree.cb
View File

@ -24,7 +24,7 @@ chip soc/intel/baytrail
register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
# LPE audio codec settings
register "lpe_codec_clk_freq" = "19" # 19.2MHz clock
register "lpe_codec_clk_freq" = "25" # 25MHz clock
register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
# SD Card controller