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soc/intel/common/graphics: Add another Meteor Lake device ID 

Add 0x7d55 as another ID for Meteor Lake graphics controllers.

TEST=Boot with MTL silicon to check coreboot log for DID2
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Iea01f6d4f2469fc0eeac73a3f1c4b9af1f39463c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This commit is contained in:
Wonkyu Kim 2022-07-04 20:43:47 -07:00 committed by Felix Held
parent b858f2e5c9
commit 25c2075388
3 changed files with 4 additions and 1 deletions
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3
src/include/device/pci_ids.h
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@ -4009,7 +4009,8 @@
#define PCI_DID_INTEL_ADL_N_GT3 0x46D2 #define PCI_DID_INTEL_ADL_N_GT3 0x46D2
#define PCI_DID_INTEL_MTL_M_GT2 0x7d40 #define PCI_DID_INTEL_MTL_M_GT2 0x7d40
#define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_1 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d60 #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d60
#define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0

1
src/soc/intel/common/block/graphics/graphics.c
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@ -186,6 +186,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_M_GT2, PCI_DID_INTEL_MTL_M_GT2,
PCI_DID_INTEL_MTL_P_GT2_1, PCI_DID_INTEL_MTL_P_GT2_1,
PCI_DID_INTEL_MTL_P_GT2_2, PCI_DID_INTEL_MTL_P_GT2_2,
PCI_DID_INTEL_MTL_P_GT2_3,
PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_505,
PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_APL_IGD_HD_500,
PCI_DID_INTEL_CNL_GT2_ULX_1, PCI_DID_INTEL_CNL_GT2_ULX_1,

1
src/soc/intel/meteorlake/bootblock/report_platform.c
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@ -51,6 +51,7 @@ static struct {
{ PCI_DID_INTEL_MTL_M_GT2, "MeteorLake-M GT2" }, { PCI_DID_INTEL_MTL_M_GT2, "MeteorLake-M GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_1, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_1, "MeteorLake-P GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" },
{ PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" },
}; };
static inline uint8_t get_dev_revision(pci_devfn_t dev) static inline uint8_t get_dev_revision(pci_devfn_t dev)