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soc/intel/skylake: Disable s0ix if not enabled in devicetree 

There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:

- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP

BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10

Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Duncan Laurie 2017-02-17 17:16:43 -08:00 committed by Martin Roth
parent c9db384ea4
commit 25c7d9342b
2 changed files with 1 additions and 3 deletions
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3
src/soc/intel/skylake/acpi.c
View File

@ -146,9 +146,6 @@ static int cstate_set_non_s0ix[] = {
C_STATE_C1E,
C_STATE_C3,
C_STATE_C7S_LONG_LAT,
C_STATE_C8,
C_STATE_C9,
C_STATE_C10
};
static int get_cores_per_package(void)

1
src/soc/intel/skylake/chip_fsp20.c
View File

@ -205,6 +205,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
params->PchPmSlpS0Enable = config->s0ix_enable;
params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;