mb/google/brya/var/agah: Update PEXVDD enable GPIO for next board rev

The next rev of this board will move the dGPU PEXVDD enable pin from
GPP_E10 to GPP_F12. This patch handles both the old and newer revisions
by using an ACPI Name to hold the GPIO # for PEXVDD enable. It also
cleans up the GPIO handling a little bit between board revs.

BUG=b:242752623
TEST=dGPU is functional and power sequencing tests still pass on board
rev 2

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icc7968777f86ab07561b0a861b7d22ec714d1c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/mainboard/google/brya/acpi/power.asl

@@ -10,7 +10,7 @@ External (\_SB.PCI0.PMC.IPCS, MethodObj)
 #define GPIO_NV33_PWR_EN	GPP_A21
 #define GPIO_NV33_PG		GPP_A22
 #define GPIO_NVVDD_PWR_EN	GPP_E0
-#define GPIO_PEXVDD_PWR_EN	GPP_E10
+#define GPIO_PEXVDD_PWR_EN	GPP_F12
 #define GPIO_PEXVDD_PG		GPP_E17
 #define GPIO_FBVDD_PWR_EN	GPP_A19
 #define GPIO_FBVDD_PG		GPP_E4
@@ -31,13 +31,17 @@ External (\_SB.PCI0.PMC.IPCS, MethodObj)
 #define GPU_POWER_STATE_ON	1
 
 /*
- * For board revs 3 and later, the PG pin for the NVVDD VR moved from
+ * For board revs 3 and later, two pins moved:
- * GPP_E16 to GPP_E3. To accommodate this, this DSDT contains a Name
+ * - The PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3.
- * that the `variant.c` code will write the correct GPIO # to depending
+ * - The enable pin for the PEXVDD VR moved from GPP_E10 to GPP_F12
- * on the board rev, and we'll use that instead.
+ *
+ * To accommodate this, the DSDT contains two Names that this code
+ * will write the correct GPIO # to depending on the board rev, and
+ * we'll use that instead.
  */
 /* Dynamically-assigned NVVDD PG GPIO, set in _INI in SSDT */
 Name (NVPG, 0)
+Name (PXEN, 0)
 
 /* Optimus Power Control State */
 Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
@@ -112,7 +116,7 @@ Method (GC6I, 0, Serialized)
 	CTXS (GPIO_GPU_ALLRAILS_PG)
 
 	/* Ramp down PEXVDD */
-	CTXS (GPIO_PEXVDD_PWR_EN)
+	CTXS (PXEN)
 	GPPL (GPIO_PEXVDD_PG, 0, 20)
 	Sleep (10)
 
@@ -149,7 +153,7 @@ Method (GC6O, 0, Serialized)
 	GPPL (NVPG, 1, 4)
 
 	/* Ramp up PEXVDD */
-	STXS (GPIO_PEXVDD_PWR_EN)
+	STXS (PXEN)
 	GPPL (GPIO_PEXVDD_PG, 1, 4)
 
 	/* Assert PG_GPU_ALLRAILS */
@@ -206,7 +210,7 @@ Method (PGON, 0, Serialized)
 	GPPL (NVPG, 1, 5)
 
 	/* Ramp up PEXVDD rail */
-	STXS (GPIO_PEXVDD_PWR_EN)
+	STXS (PXEN)
 	GPPL (GPIO_PEXVDD_PG, 1, 5)
 
 	/* Ramp up FBVDD rail (active low) */
@@ -240,7 +244,7 @@ Method (PGOF, 0, Serialized)
 	GPPL (GPIO_FBVDD_PG, 0, 20)
 
 	/* Ramp down PEXVDD and let rail discharge to <10% */
-	CTXS (GPIO_PEXVDD_PWR_EN)
+	CTXS (PXEN)
 	GPPL (GPIO_PEXVDD_PG, 0, 20)
 	Sleep (10)
 

src/mainboard/google/brya/variants/agah/gpio.c

@@ -88,7 +88,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* E9  : USB_OC0# ==> USB_A2_OC_ODL */
 	PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
 	/* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */
-	PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG),
+	PAD_CFG_GPO(GPP_E10, 0, PLTRST),
 	/* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD (before board rev 3) */
 	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
 	/* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */
@@ -106,8 +106,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC(GPP_F6, NONE),
 	/* F11 : THC1_SPI2_CLK ==> NC */
 	PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
-	/* F12 : GSXDOUT ==> NC */
+	/* F12 : GSXDOUT ==> EN_PP0950_GPU_X (board rev 3 and after) */
-	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	PAD_CFG_GPO(GPP_F12, 0, PLTRST),
 	/* F13 : GSXDOUT ==> NC */
 	PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 	/* F14 : GSXDIN ==> TCHPAD_INT_ODL */

src/mainboard/google/brya/variants/agah/variant.c

@@ -16,7 +16,7 @@
 #define NV33_PG			GPP_A22
 #define NVVDD_PWR_EN		GPP_E0
 #define NVVDD_PG		GPP_E3
-#define PEXVDD_PWR_EN		GPP_E10
+#define PEXVDD_PWR_EN		GPP_F12
 #define PEXVDD_PG		GPP_E17
 #define FBVDD_PWR_EN		GPP_A19
 #define FBVDD_PG		GPP_E4
@@ -135,29 +135,54 @@ void variant_init(void)
 	if (acpi_is_wakeup_s3())
 		return;
 
-	/* For board revs 3 and later, the power good pin for the NVVDD
+	/* For board revs 3 and later, the power good pin for the
-	   VR moved from GPP_E16 to GPP_E3, so patch up the table for
+	   NVVDD VR moved from GPP_E16 to GPP_E3, and the PEX enable
-	   old board revs. */
+	   pin moved from GPP_E10 to GPP_F12, so patch up the table
+	   for old board revs. */
 	if (board_id() < 3) {
+		const struct pad_config board_rev_2_gpios[] = {
+			PAD_NC(GPP_E3, NONE),
+			PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG),
+			PAD_CFG_GPI(GPP_E16, NONE, PLTRST),
+			PAD_NC(GPP_F12, NONE),
+		};
+		gpio_configure_pads(board_rev_2_gpios, ARRAY_SIZE(board_rev_2_gpios));
+
 		gpu_on_seq[2].pg_gpio = GPP_E16;
 		gpu_off_seq[2].pg_gpio = GPP_E16;
+
+		gpu_on_seq[3].pwr_en_gpio = GPP_E10;
+		gpu_off_seq[3].pwr_en_gpio = GPP_E10;
+	} else {
+		const struct pad_config board_rev_3_gpios[] = {
+			PAD_CFG_GPO(GPP_E3, 0, PLTRST),
+			PAD_NC(GPP_E10, NONE),
+			PAD_NC(GPP_E16, NONE),
+			PAD_CFG_GPO(GPP_F12, 0, PLTRST),
+		};
+		gpio_configure_pads(board_rev_3_gpios, ARRAY_SIZE(board_rev_3_gpios));
 	}
 
 	dgpu_power_sequence_on();
 }
 
 /*
- * For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to
+ * For board revs 3 and later, two pins moved:
- * GPP_E3. To accommodate this, the DSDT contains a Name that this code will
+ * - The PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3.
- * write the correct GPIO # to depending on the board rev, and we'll use that
+ * - The enable pin for the PEXVDD VR moved from GPP_E10 to GPP_F12
- * instead.
+ *
+ * To accommodate this, the DSDT contains two Names that this code
+ * will write the correct GPIO # to depending on the board rev, and
+ * we'll use that instead.
  */
 void variant_fill_ssdt(const struct device *dev)
 {
 	const int nvvdd_pg_gpio = board_id() < 3 ? GPP_E16 : GPP_E3;
+	const int pex_en_gpio = board_id() < 3 ? GPP_E10 : GPP_F12;
 	acpigen_write_scope("\\_SB.PCI0.PEG0.PEGP");
 	acpigen_write_method("_INI", 0);
 	acpigen_write_store_int_to_namestr(nvvdd_pg_gpio, "NVPG");
+	acpigen_write_store_int_to_namestr(pex_en_gpio, "PXEN");
 	acpigen_write_method_end();
 	acpigen_write_scope_end();
 }