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Convert i945 boards to use reserved resources instead of directly adding 

coreboot table entries in every mainboard.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2010-09-13 13:14:48 +00:00
parent 43882f1714
commit 25d1213e3f
10 changed files with 17 additions and 40 deletions
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1
src/mainboard/getac/p470/Kconfig
View File

@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
select HAVE_ACPI_SLIC
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select AP_IN_SIPI_WAIT
select UDELAY_LAPIC

5
src/mainboard/getac/p470/mainboard.c
View File

@ -98,11 +98,6 @@ static void mainboard_enable(device_t dev)
verb_setup();
}
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
struct chip_operations mainboard_ops = {
CHIP_NAME("Getac P470 Rugged Notebook")
.enable_dev = mainboard_enable,

1
src/mainboard/ibase/mb899/Kconfig
View File

@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_512

5
src/mainboard/ibase/mb899/mainboard.c
View File

@ -29,11 +29,6 @@
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{

1
src/mainboard/intel/d945gclf/Kconfig
View File

@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER

5
src/mainboard/intel/d945gclf/mainboard.c
View File

@ -23,11 +23,6 @@
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel D945GCLF Mainboard")
};

1
src/mainboard/kontron/986lcd-m/Kconfig
View File

@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_1024

7
src/mainboard/kontron/986lcd-m/mainboard.c
View File

@ -20,20 +20,13 @@
#include <types.h>
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
{

5
src/mainboard/roda/rk886ex/mainboard.c
View File

@ -134,11 +134,6 @@ static void mainboard_enable(device_t dev)
#endif
}
int add_mainboard_resources(struct lb_memory *mem)
{
return add_northbridge_resources(mem);
}
struct chip_operations mainboard_ops = {
CHIP_NAME("Roda Computer GmbH RK886EX Rugged Notebook (ROCKY3+)")
.enable_dev = mainboard_enable,

24
src/northbridge/intel/i945/northbridge.c
View File

@ -70,20 +70,26 @@ static int get_pcie_bar(u32 *base, u32 *len)
/* IDG memory */
uint64_t uma_memory_base=0, uma_memory_size=0;
int add_northbridge_resources(struct lb_memory *mem)
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
printk(BIOS_DEBUG, "Adding UMA memory area\n");
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
resource = new_resource(dev, index);
resource->base = (resource_t) uma_memory_base;
resource->size = (resource_t) uma_memory_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar\n");
get_pcie_bar(&pcie_config_base, &pcie_config_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
pcie_config_base, pcie_config_size);
return 0;
resource = new_resource(dev, index+1);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
}
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
@ -208,6 +214,8 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
add_fixed_resources(dev, 6);
assign_resources(dev->link_list);
#if CONFIG_WRITE_HIGH_TABLES==1