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soc/amd/stoneyridge: Split sata functionality 

Separate chipset-specific source from sata_init(), and modify it
to better match coreboot conventions.  A subsequent patch will
move the generic portion to soc/amd/common.

The support for enabling port multipliers appears to have been
first added for Kabini.  Although missing from the documentation,
the ability to affect the HBA Capabilities Register seems to remain
for Stoney Ridge.

Change-Id: I5dd9f613d36badc3e4d185a22b4475cb82ce187e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32660
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson 2019-05-29 09:29:12 -06:00 committed by Martin Roth
parent 19cae7c891
commit 25e5401cdd
2 changed files with 28 additions and 21 deletions
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7
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -247,6 +247,13 @@
#define GPE0_LIMIT 28 #define GPE0_LIMIT 28
#define TOTAL_BITS(a) (8 * sizeof(a)) #define TOTAL_BITS(a) (8 * sizeof(a))
/* SATA Controller D11F0 */
#define SATA_MISC_CONTROL_REG 0x40
#define SATA_MISC_SUBCLASS_WREN BIT(0)
/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */
#define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12)
/* SPI Controller (base address in D14F3xA0) */ /* SPI Controller (base address in D14F3xA0) */
#define SPI_BASE_ALIGNMENT BIT(6) #define SPI_BASE_ALIGNMENT BIT(6)

42
src/soc/amd/stoneyridge/sata.c
View File

@ -17,40 +17,40 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
static void soc_enable_sata_features(struct device *dev)
static void sata_init(struct device *dev)
{ {
/************************************** u8 *ahci_ptr;
* Configure the SATA port multiplier * u32 misc_ctl, cap_cfg;
**************************************/
#define BYTE_TO_DWORD_OFFSET(x) (x/4)
#define AHCI_BASE_ADDRESS_REG 0x24
#define MISC_CONTROL_REG 0x40
#define UNLOCK_BIT (1<<0)
#define SATA_CAPABILITIES_REG 0xfc
#define CFG_CAP_SPM (1<<12)
u32 *ahci_ptr = (void *)(uintptr_t)ALIGN_DOWN(
pci_read_config32(dev, AHCI_BASE_ADDRESS_REG), 256);
u32 temp; u32 temp;
/* unlock the write-protect */ /* unlock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG); misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
temp |= UNLOCK_BIT; misc_ctl |= SATA_MISC_SUBCLASS_WREN;
pci_write_config32(dev, MISC_CONTROL_REG, temp); pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl);
/* set the SATA AHCI mode to allow port expanders */ /* set the SATA AHCI mode to allow port expanders */
*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
|= CFG_CAP_SPM; pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256);
cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
cap_cfg |= SATA_CAPABILITY_SPM;
write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
/* lock the write-protect */ /* lock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG); temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG);
temp &= ~UNLOCK_BIT; temp &= ~SATA_MISC_SUBCLASS_WREN;
pci_write_config32(dev, MISC_CONTROL_REG, temp); pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp);
}; };
static void sata_init(struct device *dev)
{
soc_enable_sata_features(dev);
}
static struct pci_operations lops_pci = { static struct pci_operations lops_pci = {
/* .set_subsystem = pci_dev_set_subsystem, */ /* .set_subsystem = pci_dev_set_subsystem, */
}; };